Intel achieves full integration of optical I/O chips

Intel’s OCI (Optical Compute Interconnect) chiplet promises to revolutionize high-speed data processing for AI infrastructure.

Intel has made breakthrough progress in silicon photonics integration technology for high-speed data transmission. At the Optical Fiber Communications Conference (OFC) 2024, the Intel Silicon Photonics Integration Solutions (IPS) team demonstrated the industry-leading, fully integrated OCI (Optical Compute Interconnect) core, which is packaged with Intel CPUs to run real data. For data center and HPC applications, Intel's OCI core enables optical I/O (input/output) co-packaging in emerging AI infrastructure, thereby promoting innovation in high-bandwidth interconnect technology.

“Today’s data center infrastructure is straining to the limit with increasing data transfer between servers. Current solutions are rapidly approaching the practical limits of electrical I/O performance. However, with this breakthrough from Intel, customers can seamlessly integrate silicon photonics co-sealed interconnects into next-generation computing systems,” said Thomas Liljeberg, senior director of product management and strategy for Intel’s Silicon Photonics Integrated Solutions Team. “Intel’s OCI chiplets significantly increase bandwidth, reduce power consumption and extend transmission distances to help accelerate machine learning workloads, driving innovation in high-performance AI infrastructure.”

The OCI chip can support 64 32Gbps channels in one direction on optical fiber up to 100 meters long, which is expected to meet the growing demand for higher bandwidth, lower power consumption and longer transmission distance in AI infrastructure. It will help realize scalable CPU and GPU cluster connections, and new computing architectures including consistent memory expansion and resource disaggregation.

AI applications are increasingly being deployed around the world, and the recent development of large language models and generative AI is accelerating this trend. Larger and more efficient machine learning models will play a key role in the new demand for AI workload acceleration. Future computing platforms need to scale for AI, requiring exponentially higher I/O bandwidth and longer transmission distances to support larger processor (CPU, GPU, and IPU) clusters and more efficient resource utilization architectures such as xPU disaggregation and memory pooling.

Electrical I/O (i.e., copper trace connections) have high bandwidth density and low power consumption, but the transmission distance is short, less than one meter. Pluggable optical transceiver modules used in data centers and early AI clusters can extend the transmission distance, but their cost and power consumption are not sustainable in terms of the expansion needs of AI workloads. The xPU optoelectronic co-sealed I/O solution can support higher bandwidth while improving energy efficiency, reducing latency and extending transmission distance to meet the expansion needs of AI and machine learning infrastructure.

To use an analogy, replacing electrical I/O with optical I/O for data transfer in CPUs and GPUs is like moving from horse-drawn carriages (limited capacity and distance) to cars and trucks for delivering goods (larger quantities and longer distances). Optical I/O solutions such as Intel’s OCI chiplets enable this level of improvement in performance and power consumption, helping AI scale.

Intel OCI (Optical Compute Interconnect) chip

In the fully integrated OCI chip, Intel has used proven silicon photonics technology to integrate silicon photonic integrated circuits (PICs) with on-chip lasers, optical amplifiers, and electronic integrated circuits. At the 2024 Optical Fiber Communications Conference, Intel demonstrated the OCI chip packaged with its own CPU, but it can also be integrated with next-generation CPUs, GPUs, IPUs, and other SOCs (system-on-chips).

This fully integrated OCI chip has a bidirectional data transmission speed of 4 Tbps and is compatible with PCIe Gen 5. At the 2024 Optical Communications Conference, a live optical link demonstration showed the transmitter (Tx) and receiver (Rx) interconnection between two CPU platforms through a single-mode fiber (SMF) patch cord. The CPU generated and measured the bit error rate (BER). Intel also demonstrated the optical spectrum of the transmitter, including eight wavelengths spaced at 200GHz on a single fiber, and a 32Gbps transmitter eye diagram, indicating strong signal quality.

The chip currently supports 64 32Gbps channels in one direction with a transmission distance of 100 meters (due to transmission delay, the distance in actual application may be limited to tens of meters). It uses 8 pairs of optical fibers, each with 8 wavelengths of dense wavelength division multiplexing (DWDM). This co-packaged solution is also very energy-efficient, with a power consumption of only 5 picojoules (pJ) per bit, while the power consumption of pluggable optical transceiver modules is about 15 pJ per bit. Ultra-high energy efficiency is very important for data centers and HPC environments, which can help solve the high energy consumption problem of AI applications and improve sustainability.

Intel Labs has been working in the field of silicon photonics for more than 25 years and is a pioneer and leader in silicon photonics integration. Intel is the first in the industry to develop and deliver silicon photonics connection devices in batches to large cloud service providers, and these products have leading reliability.

Intel's main differentiating advantage lies in its direct integration technology, combined with on-wafer laser hybrid integration technology, which can improve yield and reduce costs. This unique approach enables Intel to achieve excellent performance while maintaining high energy efficiency. Relying on a powerful mass production platform, Intel has shipped more than 8 million silicon photonic integrated circuits, including up to 32 million on-chip integrated lasers, with a time-based failure rate (FIT) of less than 0.1. Time-based failure rate is a widely used method to measure reliability, which reflects the failure rate and the number of failures that occur.

These silicon photonic integrated circuits are packaged in pluggable transceiver modules and deployed in large data center networks of hyperscale cloud service providers for applications requiring transmission rates up to 100, 200, and 400 Gbps. Silicon photonic integrated circuits with speeds up to 200G/channel are under development for emerging applications requiring transmission rates up to 800 Gbps and 1.6 Tbps.

Intel is also exploring new silicon photonics manufacturing process nodes that offer advanced device performance, higher density, better coupling, and significantly improved economics. Intel continues to make advances in on-chip lasers and performance, cost (more than 40% reduction in chip area), and power consumption (more than 15% reduction).

Intel's OCI chip is currently in the prototype stage. Intel is working with customers to develop co-sealed OCI and customer SoCs as an optical I/O solution.

Intel's OCI chiplets have driven the advancement of high-speed data transmission technology. As AI infrastructure continues to develop, Intel will continue to promote cutting-edge technological innovation and explore future-oriented connection technologies.