Intel FPGA 2019 Engineer Application Video

New season of Intel FPGA engineer application videos! The content mainly focuses on the troubles of FPGA engineers, teaching you step by step how to solve some common problems and imparting tips.

• Chapter 1：Create a black box using blank partitions in quartus® prime pro (3 minutes and 52 seconds)

• Chapter 2：How to fix recovery timing confusion related to asynchronous reset - Part 1 (5 minutes and 2 seconds)

• Chapter 3：How to fix recovery timing confusion related to asynchronous reset - Part 2 (4 minutes and 24 seconds)

• Chapter 4：Run u-boot script on stratix® 10 soc fpga (2 minutes and 54 seconds)

• Chapter 5：How to perform integrity check in arria® 10 hard ip pci express (3 minutes and 50 seconds)

• Chapter 6：How to run arria 10 ddr4 design in infinite loop (3 minutes and 16 seconds)

• Chapter 7：How to Implement Intel Cyclone 10 GX ATX PLL Reference Clock Switching Dynamic Reconfiguration (4 minutes and 8 seconds)

• Chapter 8：How to implement cyclone 10 gx dynamic reconfiguration (with fpll switching) and channel reconfiguration (using direct write method) (3 minutes and 54 seconds)

• Chapter 9：How to implement cyclone 10 gx native phy atx pll switching and channel reconfiguration using embedded streamer (4 minutes and 0 seconds)

• Chapter 10：How to encrypt using the ieee1735 standard encrypt_1735 utility in quartus® prime pro (4 minutes and 41 seconds)

• Chapter 11：How to read chip id in embedded system using nios® ii and hard processor system (hps) (3 minutes and 50 seconds)

• Chapter 12：Introducing the Intel® FPGA Stratix® 10 Reference Board Support Package Directory Structure (11 minutes and 47 seconds)