Hejian Software and Open Source Chip Research Institute deepen strategic technical cooperation to enable the construction of large-scale systems of "Xiangshan" open source RISC-V processors

Hejian Software and Open Source Chip Research Institute deepen strategic technical cooperation to enable the construction of large-scale systems of "Xiangshan" high-performance open source RISC-V processors

August 21, 2024 - Shanghai Shanghai Hejian Industrial Software Group Co., Ltd. (hereinafter referred to as "Hejian Industrial Software") and Beijing Open Source Chip Research Institute (hereinafter referred to as "Open Source Institute") have deepened their strategic technical cooperation on the "Xiangshan" high-performance open source RISC-V processor project, and applied Hejian Industrial Software's commercial-grade full-scenario verification hardware system UniVista Unified Verification Hardware System (hereinafter referred to as "UVHS") to improve the development and verification efficiency of the "Xiangshan" high-performance open source RISC-V processor, promote innovation and accelerate the time to market of next-generation product technologies.

The "Xiangshan" high-performance open source RISC-V processor was developed by the Beijing Open Source Chip Research Institute and quickly became an innovation leader in the RISC-V ecological community. The Xiangshan project aims to promote the development of high-performance open source processors in China. With the help of the RISC-V instruction set architecture (ISA), Xiangshan has developed three generations of processors and has gained wide recognition and respect in the RISC-V community. Its innovative design and high performance make it a reference design for high-performance RISC-V implementations, and it has won many honors at many top international summits.

Hejian Software worked closely with OpenCore Research Institute to successfully apply Hejian Software's full-scenario verification hardware system UVHS in the development of the second-generation "Nanhu" and third-generation "Kunming Lake" processors and the optimization of the software ecosystem, significantly improving development efficiency.

• Automatic segmentation technology and clock conversion technology simplify platform migration costs: The flexible scalability of the "Xiangshan" processor requires that large multi-core designs can be segmented onto multiple FPGAs. UVHS's automatic segmentation technology fully automates the entire process, and its powerful clock conversion engine can automatically handle multiple asynchronous clocks within the design, greatly simplifying the manual work of engineers and making it easier to quickly migrate ASIC-style RISC-V RTL code to the FPGA platform. It took less than a week to import the dual-core RTL code of "Xiangshan" to achieve Linux OS startup on UVHS.

• High operating performance significantly shortens software running time: Based on Xilinx's new FPGA platform, UVHS system's global timing-driven intelligent automatic segmentation technology can push operating performance to a higher level, thereby optimizing the software development project cycle with higher efficiency.

• Rich debugging methods: UVHS system supports UHD infinite depth waveform debugging, triggering, asynchronous register readback and other functions, similar to the waveform debugging function of simulation mode, which significantly improves the debugging efficiency and problem location ability. DDR and SRAM backdoor access also greatly increases the convenience of user debugging.

At the same time, UVHS large-scale system cascade can cascade up to tens of billions of logic gates. It has been successfully deployed in many commercial customers, achieving the cascade of up to 160 VU19P FPGAs, meeting the needs of HPC ultra-large system scale verification, and providing reliable technical support for Xiangshan's future RISC-V large-scale system expansion.

On the other hand, UVHS is equipped with a wealth of high-speed interface and storage model solutions, supporting multiple rate adapter solutions such as PCIe Gen5, MIPI CSI2/DSI2, Ethernet 1G-800G, as well as storage models such as DDR5, DDR4, LPDDR5, LPDDR4, HBM3, etc., which can help users of the RISC-V ecosystem quickly build a complete verification scenario.

Wu Xiaozhong, Vice President of Hejian Software Co., Ltd. said: "Xiangshan processors have made important innovative contributions to the development of the RISC-V ecosystem. We are very proud to support OpenCore Institute through the UVHS hardware acceleration platform to help them accelerate project development and improve design stability. UVHS is an innovative high-performance, large-capacity, full-scenario verification hardware acceleration platform designed to cope with today's complex and diverse SoC software and hardware verification tasks. Based on our successful deployment experience in large chip projects of many customers, we look forward to continuing to help Xiangshan processors achieve project convergence more efficiently in large system design and development, and work with Xiangshan to contribute productivity tools to the RISC-V ecosystem."

Future Directions and Innovations

The cooperation between Hejian Software and OpenCore Institute on the "Xiangshan" project marks an important milestone in the RISC-V ecosystem. By combining the "Xiangshan" innovative processor design with Hejian Software's advanced verification technology, the development of high-performance open source RISC-V processors can be accelerated. At the same time, the cooperation between Hejian Software and OpenCore Institute will further promote innovation in the RISC-V ecosystem:

-Multi-core large processor verification

As the multi-core scale and complexity of RISC-V processors increase, the interaction and consistency issues between multiple cores become more complicated, including memory consistency and cache consistency. Verification tools and methods need to be able to execute operations on multiple cores simultaneously and compare expected results to ensure the correctness and performance of multi-core systems in various situations. Hejian Software will further maintain in-depth technical cooperation with OpenCore Institute in this regard.

-CPU debugging tools

As Xiangshan pushes the limits of RISC-V performance, the complexity of design verification grows exponentially. Ensuring the correctness of advanced features such as out-of-order execution, speculative execution, and complex cache hierarchies requires complex verification methods and tools. General and convenient processor debugging tools can comprehensively analyze, optimize, and verify all stages from single-core to multi-core systems, and can also promote technology and efficiency innovation for the entire ecosystem. Relying on the experience of developing other CPU ecosystems, Hejian Gongsoft will explore and develop new tools in the RISC-V field with OpenCore Institute.

-Performance testing and optimization

In order to achieve industry-competitive performance levels, the processor's microarchitecture, bus architecture, and storage performance must be continuously optimized. The entire process requires extensive testing and verification under various workloads and usage scenarios to ensure that the processor system can operate stably and efficiently under different conditions. The hardware platform verification solution provided by Hejian Gongsoft can cover the testing and verification of common application scenarios, while coping with extreme and unexpected operating conditions to ensure the robustness and reliability of the processor.

- Ecosystem expansion

The success of the cooperation between Hejian Gongsoft and Xiangshan will attract more partners to join the RISC-V ecosystem. By establishing a strong support ecosystem, including localized documentation, developer portals and application examples, it can promote the application and innovation of RISC-V in various fields. Through these optimizations and corrections, the complexity of current multi-core processor design and verification, as well as the tools and methods required, are more accurately reflected.