Computer composition and design: RISC-V (Zhejiang University)

  This course is a professional basic course for information and electronic engineering and related computer majors. The course includes processor RISC-V instruction set, addressing mode, data types, assembly language, processor microstructure, controller and pipeline, storage system, cache , virtual storage, multi-processor and parallel technology, system design performance evaluation and software and hardware co-design methods, etc.

This course can be combined with offline teaching to provide students with an online platform for review, Q&A and self-evaluation, further consolidating and expanding the content learned in the classroom, and strengthening communication between students and teachers outside the classroom; it can also serve as a Online learning resources for undergraduates in information engineering and computer-related majors in colleges and universities to study courses such as "Computer Composition and Design" and "Computer System Structure"; and can be used as a reference for computer-related professionals and relevant teachers in colleges and universities.

This course is based on the interpretation and teaching of RISC-V instruction set architecture. While mastering the traditional computer composition knowledge, you can also learn to understand the instruction set and system architecture design methods.

• Chapter 1：Course introduction video (11 minutes and 33 seconds)

• Chapter 2：arithmetic instructions (14 minutes and 25 seconds)

• Chapter 3：memory access instructions (11 minutes and 23 seconds)

• Chapter 4：Conditional branch transfer instructions (8 minutes and 34 seconds)

• Chapter 5：Logical operation instructions (7 minutes and 16 seconds)

• Chapter 6：function call (10 minutes and 18 seconds)

• Chapter 7：Stack usage (14 minutes and 13 seconds)

• Chapter 8：R type instruction (12 minutes and 11 seconds)

• Chapter 9：I-type instructions and S-type instructions (11 minutes and 32 seconds)

• Chapter 10：B type instruction and U type instruction (13 minutes and 7 seconds)

• Chapter 11：J type command (10 minutes and 37 seconds)

• Chapter 12：Basic unit module of data path (13 minutes and 23 seconds)

• Chapter 13：R-Type Instructions and I-Type Arithmetic Instructions Video (12 minutes and 16 seconds)

• Chapter 14：I-type memory access instructions and S-type instructions (12 minutes and 34 seconds)

• Chapter 15：B type instruction, I type JALR instruction, J type instruction, U type instruction (14 minutes and 49 seconds)

• Chapter 16：control signal, critical path (14 minutes and 59 seconds)

• Chapter 17：Controller implementation (6 minutes and 31 seconds)

• Chapter 18：Processor performance (14 minutes and 21 seconds)

• Chapter 19：Assembly line design and structural adventures (10 minutes and 4 seconds)

• Chapter 20：data adventure (10 minutes and 33 seconds)

• Chapter 21：Control Adventure and Superscalar Processors (16 minutes and 41 seconds)

• Chapter 22：memory hierarchy (11 minutes and 30 seconds)

• Chapter 23：direct map cache (16 minutes and 12 seconds)

• Chapter 24：access and absence (16 minutes and 54 seconds)

• Chapter 25：Cache design optimization (18 minutes and 30 seconds)

• Chapter 26：Operating system and virtual storage (12 minutes and 36 seconds)

• Chapter 27：page table (15 minutes and 14 seconds)

• Chapter 28：Address translation cache I (15 minutes and 59 seconds)

• Chapter 29：Address Translation Cache II (6 minutes and 37 seconds)

• Chapter 30：Single instruction stream, multiple data streams (13 minutes and 6 seconds)

• Chapter 31：Multiple instructions and multiple data streams (13 minutes and 50 seconds)

• Chapter 32：Thread-level parallel programming (16 minutes and 15 seconds)

• Chapter 33：Hardware synchronization (9 minutes and 51 seconds)

• Chapter 34：shared memory multiprocessor (11 minutes and 54 seconds)