Design of TACAN video signal generation circuit based on PCI bus

The PCI bus has the advantages of supporting multiple peripheral devices, being independent of the processor, and having fast data transmission. It has been applied to various occasions such as PCs and industrial computers. For example, data acquisition cards, IO control cards, bus cards, etc. all use the PCI bus structure. When designing a comprehensive test system, in order to improve the requirements of system integration and modularization, a TACAN video signal generation board based on PCI9054 was designed and developed.

1 System composition and design requirements

The system is mainly composed of power supply, PCI interface, FPGA logic, DSP, D/A conversion and other circuits. Among them, the power supply circuit provides power for the entire circuit board, the PCI interface circuit provides a channel for information exchange between the PC and the circuit board, the FPGA is responsible for the logic of the entire circuit system, the DSP circuit is responsible for the data operation of the entire circuit system, and the D/A conversion circuit converts the envelope data generated by the DSP into an analog signal. The system structure of the TACAN video signal generation circuit is shown in Figure 1.

The working process of the TACAN video signal generation circuit is as follows: PC sends control instructions through the PCI interface circuit, FPGA receives control instructions through the PCI9054 device and transmits the instruction information to DSP. After receiving the instruction information, DSP generates corresponding operations, and the D/A conversion circuit converts the envelope data generated by DSP into analog signals and transmits them. The TACAN video signal generation circuit will generate a sine envelope signal and a reference signal that meet the requirements. Among them, the sine envelope signal mainly includes a 15 Hz sine envelope signal and a 135 Hz sine envelope signal, and its function is:

In the formula, f=15 Hz, A0 is the DC component, A1 and A2 are the amplitudes of the 15 Hz sine envelope and the 135 Hz sine envelope respectively. At the same time, the system can also generate a main reference pulse group when generating a 15 Hz sine envelope, and generate an auxiliary reference pulse group when generating a 135 Hz sine envelope. The azimuth information can be determined by the proportion of the time interval between the reference pulse group signal and the zero-crossing point of the positive slope of the sine envelope in the total time of the sine envelope.

Combined with the test requirements of a certain type of TACAN, the specific design requirements of the system are: the signal depth of the 15 Hz and 135 Hz sinusoidal envelopes are both adjustable, the amplitude adjustment range is 0~40%, and the minimum adjustment interval is 1%; the sum of the amplitudes of the 15 Hz sinusoidal envelope and the 135 Hz sinusoidal envelope does not exceed 40% of the total envelope amplitude; the phase of the 15 Hz sinusoidal envelope is adjustable within 0°~359.9°, and the minimum adjustment interval is 0.1°; the phase of the 135 Hz sinusoidal envelope is adjustable within 0°~39.9°, and the minimum adjustment interval is also 0.1°.

2 System Hardware Circuit Design

2.1 Power supply circuit

The main function of the power supply circuit is to provide power for the entire circuit board system. The power supply circuit takes 3.3 V and 5 V power from the PCI slot, and can obtain 1.8 V and 1.2 V voltages respectively through voltage converters LD1117S18 and LD1117S12 for different devices.

2.2 PCI interface circuit

The main function of the PCI interface circuit is to provide a channel for information exchange between the PC and the TACAN video signal generation circuit. The PCI9054 device of PLX Company is selected. This device complies with the PCI local bus specification version 2.2. The burst transmission rate can reach 132 MB/s. The local bus supports multiplexed/non-multiplexed 32-bit address/data, and supports master mode, slave mode and DMA transmission mode. This device has high reliability, is easy to develop, and meets the requirements of the system.

PCI9054 is configured by booting EEPROM, and its interface circuit with serial EEPROM (IDT70261) is shown in Figure 2. PCI9054 provides 4 pins to connect with serial IDT70261, which are EEDI, EEDO, EESK, and EECS, corresponding to the DI, D0, SK, and CS pins of IDT70261. At power-on reset, PCI9054 will boot from EEPROM and configure registers to complete command control and address mapping.

The interface of the PCI9054 local bus is not fully compatible with the DSP, and data transmission needs to be realized through the FPGA. Therefore, a dual-port RAM is built inside the FPGA, and the local data line LD[15..0] and local address line LA[14..0] of the PCI9054 are directly connected to the FPGA. At the same time, the local control line of the PCI9054 is also directly connected to the FPGA, as shown in Figure 2.

2.3 FPGA Logic Circuit

The function of the FPGA circuit is to be responsible for the logic of the entire circuit system. Here, the EP2C8 device of ALTERA is selected. The device has 8 256 logic units, 36 embedded M4K RAM blocks, and supports up to 128 user IO pin resources, which fully meets the design needs. EP2C8 is equipped with two download ports: JTAG debug interface and AS mode download port. The AS mode uses the serial configuration device EPC-S4 with a storage capacity of 4 Mbit.

2.4 DSP Circuit

The DSP circuit is the data operation unit of the entire circuit system. The TI TMS320VC5416 DSP is selected, which has a built-in 128K×16 bit RAM and 16K×16 bit ROM, as well as a 40-bit arithmetic logic unit. Its main frequency can reach 160 MHz, which meets the design requirements.

As the data operation center, DSP needs to pass the calculated data to FPGA, which performs related operations. Therefore, the DSP's data line A[15:0], address line D[15:0], and other control lines are directly connected to FPGA, and DSP downloads the program through the JTAG port. The DSP interface circuit is shown in Figure 3.

2.5 D/A conversion circuit

The function of the D/A conversion circuit is to convert the envelope data generated by the DSP into an analog signal. The 12-bit parallel high-speed D/A converter AD9762 from ADI is selected, and its maximum data refresh rate is 125 MS/s. The D/A conversion circuit is shown in Figure 4.

3 System Software Design

3.1 FPGA Function Implementation

Altera integrated development platform Quartus II 6.0 was used for FPGA development. Seven functional modules including dual-port RAM, bus control, address decoding, D/A converter control, pulse sequence generation, channel control and inquiry signal detection were developed using VHDL language. They are: 1) Design dual-port RAM to realize the exchange of PCI9054 data and DSP data; 2) Implement PCI9054 local bus logic control, such as read and write logic of dual-port RAM; 3) Implement DSP address decoding logic, select different functional units according to different instructions; 4) Implement D/A converter logic control; 5) Generate pulse sequence. According to needs, reference pulse, filling pulse, response pulse and random pulse can be generated to form a pulse sequence; 6) Implement channel control and attenuation control; 7) Implement the detection of inquiry signal, etc. The internal logic of FPGA is shown in Figure 5.

3.2 DSP Programming

The DSP on-chip program uses CCS2.0 as the development platform, and mainly includes device initialization program, system initialization program, envelope data (composed of 15 Hz and 135 Hz sine signals) generation program, INTO interrupt program, INT1 interrupt program and timer interrupt program. Among them, the device initialization program completes the initialization of the on-chip peripherals (such as the setting of the phase-locked loop clock generator parameters, the setting of the timer parameters, the setting of the maskable interrupt, etc.); the system initialization program completes the initialization of the entire system (I0 address allocation, initialization setting of global variables and initialization of system peripherals); the envelope data generation program mainly generates two function tables, the 15 Hz sine data table and the 135 Hz sine data table; the INT0 interrupt program completes the reception of PC instructions: the INT1 interrupt mainly completes the response function after receiving the inquiry signal; the timer interrupt program completes the search of the function table and generates envelope data through calculation, starts the D/A conversion circuit to generate the envelope signal, and generates the pulse selection signal at the same time to control the FPGA to output the pulse sequence. The DSP main program flow is shown in Figure 6. The TACAN envelope signal waveform is shown in Figure 7.

3.3 PCI driver development

According to the driver model provided by Windows, a WDM driver was written using VC++6.0 and DriverStudio software. This driver plays the role of memory mapping and interrupt management for PCI9054. After the driver is installed, the application can access the PCI card by calling the WindowsAPI function CreateFile(). In this way, the operation of the port is ultimately manifested as the operation of a file.

4 Conclusion

Aiming at the modular design requirements of the system, a TACAN video signal generation board based on PCI9054 was developed. The TACAN video signal generation circuit based on PCI bus is applicable to a variety of industrial computer platforms, has strong versatility, meets the design requirements, and has good actual use effects, so it has good application prospects.