Design of Multi-channel Synchronous Signal Source Based on DDS Technology

Realizing multi-channel synchronous output of signal sources has important applications in radar, communication and other fields. In order to achieve this function, most designs use multiple dedicated DDS chip peripherals with the help of a single-chip microcomputer to achieve multi-signal synchronous output, as shown in Figure 1.

When the system is working, according to the keyboard input, the single-chip microcomputer outputs the frequency control word, phase control word and waveform selection word, controls the dedicated DDS chip AD9854 to generate a waveform with a specific frequency and phase, and outputs the required analog waveform after filtering and amplification. In order to output multiple synchronous signals with the same frequency and related phases, the control data is input by the keyboard, and the single-chip microcomputer outputs the same frequency control word and different phase control word instructions to each dedicated DDS chip, and controls each dedicated DDS chip to output the specified frequency and phase waveform. In this way, the continuous adjustment and synchronization of frequency and phase are realized as a whole.

AD9854 is a DDS series product of AD Company in the United States, with good performance and wide frequency adjustment range. In such a design, AD's AD9854 chip is used. Although it has the characteristics of wide frequency adjustment range, rich waveforms, and easy frequency modulation, it is difficult to achieve the same parameters of each chip because it uses a discrete dedicated DDS chip. The difference in parameters will cause the output signal frequency and phase to be different. Therefore, although each DDS chip uses the same frequency word, it is difficult for each output signal frequency to be completely the same. Similarly, due to the inconsistency of parameters, the phase between waveforms is difficult to adjust accurately. More importantly, the cumulative effect of the frequency differences of each signal may cause synchronization failure. In addition, dedicated DDS chips are expensive and the design cost is also high.

Based on the above reasons, a design scheme of a multi-channel synchronous signal source based on a single-chip FPGA is given here. This scheme has the advantages of simple implementation, good synchronization, and low cost.

1 Design model of multi-channel synchronous signal source based on FPGA technology

The overall block diagram of the multi-channel synchronous signal source based on FPGA technology is shown in Figure 2.

In this block diagram, taking three-way output as an example, three DDS-based signal channels are implemented in one FPGA chip, completing the functions that are traditionally completed by three dedicated DDS chips AD9854, realizing the digital output of three waveforms, and performing D/A conversion after the digital signal output to realize the analog output of three signals. The frequencies of the three DDS channels are taken from the address value output by the same accumulator, and the table is looked up. At the same time, the phase addition is also implemented for the address output by the same accumulator, eliminating the calculation error of the discrete dedicated DDS chip. Since it is implemented in one chip, the parameters of each DDS channel are consistent, and the delay error caused by the external connection of the discrete dedicated DDS chip is also minimized. Therefore, through the above measures, the consistency of the signal can be greatly improved, and accurate phase continuous adjustment can be achieved.

The single-chip computer and bus configuration circuit realize the human-machine interface through the keyboard. Through the 4×4 matrix keyboard, the frequency selection, initial phase selection and other data can be input into the single-chip computer and sent to the FPGA after being processed by the single-chip computer to realize the adjustment of DDS.

FPGA is the core component for completing the generation of DDS multi-signals and completing the generation of DDS multi-channel synchronous signals.

2 FPGA core design of multi-channel synchronous signal output based on DDS technology

2.1 General working principle of DDS

DDS (Direct Digital Synthesizer) is a frequency synthesis technology that directly synthesizes the required waveform based on the concept of phase. A DDS signal generator consists of: phase accumulator, waveform number ROM table, D/A converter and analog low-pass filter LPF. The principle block diagram is shown in Figure 3. The core of DDS technology is the phase accumulator. The phase accumulator generates the address value of the read data under the control of a stable clock signal. Then, through table lookup, the address value is converted into a digital amplitude sequence of the signal waveform. The digital/analog converter (D/A) converts the digital sequence representing the waveform amplitude into an analog voltage. Finally, the step waveform output by the D/A is smoothed into the required continuous waveform through a low-pass filter. The phase accumulator accumulates with a step length F under the control of the clock Fc. The output value is added to the phase control word P to form the address value of the table lookup, and the waveform ROM is addressed. The output value of the waveform ROM is the amplitude value, which forms a step waveform after D/A conversion, and finally is smoothed into the required waveform through a low-pass filter. The waveform of the synthesized signal depends on the amplitude sequence in the ROM table. Any waveform can be generated by modifying the data. If multiple waveforms are to be generated, the required multiple waveform data can be stored in the waveform ROM table. The schematic diagram of the general DDS principle is shown in Figure 3.

2.2 Working principle of synchronous multi-channel output DDS

The schematic diagram of the working principle of synchronous multi-channel output DDS is shown in Figure 4.

As can be seen from the block diagram, the address value output from the same phase accumulator is added with different phase words as needed before the table lookup, and then the table lookup is performed according to the new address, so as to form the phase value required between the waveforms. Since each output signal is the phase addition of the address output by the same accumulator in the DDS, the parameters are consistent and the phase adjustability is very good. The frequency is taken from the same frequency word, and each signal has a fixed synchronous and co-frequency characteristic, so the output signal source synchronization performance is excellent and fully meets the design requirements.

2.3 Design of Phase Accumulator

The phase accumulator is the core component of the DDS design. The phase accumulator of this design is composed of a 32-bit adder and a 32-bit register cascaded. The accumulator feeds back the phase data generated by the adder after the previous clock to the input end of the adder; the adder continues to add with the frequency control word (K) under the next clock to achieve phase accumulation. When the accumulated result of the phase accumulator is equal to or greater than 232, an overflow will occur, returning to the initial state, and completing a periodic waveform output. The accumulator of this design is designed and implemented in VHDL language [quartus6.0] as follows:

32-bit accumulator module implementation:



2.4 Design of waveform memory

Use the data output by the phase accumulator as the sampling address of the waveform memory, and perform the phase-code conversion of the waveform to determine the sampling amplitude code of the output waveform at a given time. This design uses FPGA resources to construct a 10-bit ROM for data storage and conversion.

ROM can be easily obtained by using the Quartus plug-in manager Megawizard plug-in manager. Here is a C program for generating sine waveform data to generate data stored in ROM. To generate data of other waveforms, you only need to simply modify the waveform expression.



3 Simulation and debugging

After analyzing and synthesizing this design in Quartus Ⅱ, the structure of the phase-adjustable multi-output DDS is shown in Figure 6.

In Quartus Ⅱ, input control signal: Fo=100 MHz, fword=50, pword=35, and simulate. The simulation result is shown in Figure 7. The simulation data generated in Quartus has been verified to be completely correct, and the amplitude data sequence of three sine waves with the same frequency and adjustable phase is obtained, which fully meets the design requirements.

4 Conclusion

This design uses VHDL hardware programming language and DDS technology, combined with FPGA high-speed devices, to achieve synchronous output of multiple signals, which well solves the problem of requiring the same frequency and adjustable phase between signals, and has the advantages of easy program control, continuous phase, high output frequency stability, high resolution, etc., and uses one FPGA block to solve the problem that traditionally requires three DDS to solve, which also greatly reduces the design cost.