Implementing ADC using FPGA and CPLD digital logic

Designers of digital systems are adept at gluing together various processors, memories, and standard functional components on their printed circuit boards using FPGAs and CPLDs to implement digital designs. In addition to these digital functions, FPGAs and CPLDs can also implement common-mode functions using LVDS inputs, simple resistor-capacitor (RC) circuits, and some of the FPGA or CPLD's digital logic cells to build analog-to-digital converters (ADCs).

ADC is a commonly used analog functional block when interfacing with digital logic, for example, FPGA or CPLD to the real world of analog sensors. This article will describe the implementation of low frequency (DC to 1K Hz) and high frequency (up to 50K Hz) ADC using reference designs and demonstration boards from Lattice Semiconductor. Application examples for each design, namely, systems in network switches and frequency detection in voice communication systems, will be verified in the article.

Implementation of analog-to-digital converter

A simple analog-to-digital converter can be implemented by adding a simple RC circuit to the LVDS input of an FPGA or CPLD. As shown in the lower left corner of Figure 1, the RC network is at one end of the LVDS input and the analog input is at the other end. The LVDS input will act as a simple analog comparator and will output a digital "1" if the analog input voltage is higher than the voltage of the RC network. By varying the input voltage of the RC circuit (which comes from the general purpose output of the FPGA/CPLD), the LVDS comparator can be used to analyze the analog input voltage to create an accurate digital representation.

The analog-to-digital control block can be implemented in a variety of ways, depending on the frequency of the analog input, the required resolution, and the available logic resources. Low frequency signals can be processed using a simple successive approximation register, as shown in option 1 in the upper left corner of Figure 1. Higher frequencies can be achieved using a delta-sigma modulator function, shown in the upper right corner of Figure 1, which consists of a sampling register and a cascaded comb (CIC) filter.

Once the digital signal is constructed, the digital output can be optionally filtered to remove any unwanted high frequency components introduced by system noise or feedback jitter. Following the optional digital filtering block, an optional memory buffer can be used for debug/test purposes. The digital output is sampled through the memory buffer and then scanned out through the JTAG port to a personal computer running signal analysis software.

Figure 1: Basic block diagram of an analog-to-digital converter: low-frequency and high-frequency cases. [page]

Low frequency/minimal logic ADC implementation

In the case of a low frequency/minimal logic implementation, the sampling control block controls the successive approximation register, and the associated output signal is applied to the RC circuit at any time. Therefore, the voltage of the RC circuit rises or falls in response to the associated output state, and the output state is changed. The LVDS input compares the analog input with the change in the RC circuit voltage. Therefore, the voltage of the RC circuit is used to "see" the analog input voltage. In the example of Figure 2, the static analog input (represented by the orange dashed line) is set to less than half of the full input voltage range. The vertical black dashed line represents the number of clocks between SAR sampling points, represented by the green dashed line.

The first measurement requires 8 clocks, the next 4 clocks, and so on. Initially, the RC circuit is set to half the full voltage swing of the analog input by placing a logic "1" on the associated output. Once the voltage reaches halfway to this point, the output of the LVDS input will indicate whether the analog input value is above or below the RC circuit voltage.

If the analog voltage is higher, the most significant bit of the digital output is a logic "1". If the analog voltage is lower, the digital output is a logic "0". The SAR moves to the next bit and the sampling time is halved (to one-quarter of the full voltage swing). This process repeats until the A/D converter achieves the desired accuracy. In the example in Figure 2, observe how the RC circuit voltage gradually approaches the analog input value. In this simple example, the 4-bit digital output of the SAR (0101) is shown at the bottom of the figure.

Figure 2: Example of a SAR-based A/D converter in action.

The low-frequency design can be used to monitor several analog voltage levels that represent various supply voltages and environmental sensor outputs. The CPLD implementation can monitor the PCB's supply voltages (3.3V, 2.5V, and 1.8V), as well as temperature and humidity sensors and open chassis alarms. To measure multiple analog inputs, one LVDS input can be used for each analog voltage along with additional RC circuits. Because the analog voltages are slowly changing, the LVDS outputs can be multiplexed so that digital logic functions can be shared between each input. [page]

Test Results for Low Frequency/Minimum Logic ADCs

The low frequency/minimal logic circuit without the optional digital filtering circuit has been implemented on a Lattice MachXO CPLD using an evaluation board and a 0.8Hz input signal with a voltage range of 0V to 3.3V. As shown in Figure 1, the optional memory buffer and the Reveal Logic Analyzer feature of the Lattice ispLEVER design software are used. This feature adds buffer memory to the target design and adds the logic required to control digital signal acquisition, data buffering, and output data to the computer via the JTAG cable. During testing, an FFT was run on the captured data using Linear's PScope software. The circuit's response to a 0.8Hz analog input is shown in the upper half of Figure 3.

Figure 3: Example of A/D converter results: low-frequency and high-frequency options.

The received digital signal is displayed in the top window of the PScope screen. The vertical axis measures code steps (0 to 255) and the horizontal axis measures samples (1024 samples in this example). The frequencies are reported in the upper right corner of the sidebar, such as the f1 (fundamental) frequency. The results of the FFT are displayed in the lower part of the window, with the harmonic frequencies displayed along the vertical axis according to their dB levels. Key parameters generated from the FFT are displayed in the lower right sidebar, including the effective number of bits (ENOB) and signal-to-noise ratio (SNR). These results show that the input signal has been successfully converted to a digital signal with good resolution and signal-to-noise ratio.

Implementing higher frequency ADCs

The front end of the higher frequency ADC in the upper right corner of Figure 1 still uses an RC circuit and LVDS input. The oversampling flip-flop captures the comparison result of the LVDS input. This signal is fed back through the common LVCMOS output that drives the RC circuit. If the comparator output is a logic "1", it means that the analog input is higher than the voltage of the RC circuit. The logic "1" is sampled by the flip-flop and fed back to the RC circuit, causing the voltage of the RC circuit to rise. If the comparator output is a logic "0", the feedback signal will be a logic "0", which will cause the RC voltage to be lower. Through this simple feedback mechanism, the digital value "tracks" the analog input frequency.

The lower right side of Figure 4 shows an example of a sampled analog input waveform, shown in red, and the output of a sampled flip-flop: the blue column represents a logic “1” and the white column represents a logic “0.” Note how the “1” and “0” change in the common pulse code modulation (PCM) format.

Using a Cascaded Integrator Comb (CIC) filter, PCM input data can be converted into an output stream that reflects the frequency of the analog input stream. The CIC function basically integrates (adds or subtracts) the single bit PCM signal to produce a continuous output signal with the desired number of bits. In the example in Figure 4 below, considering the blue bit as a "1" and the white bit as a "-1", it can be clearly seen that the summation (integration) operation will produce a digital representation of the input waveform. (Note that the output waveform will be shifted by approximately half a cycle because a sequence of "1"s will correspond to an increase in digital value. In Figure 4, the sequence of "1"s is produced in the "high" portion of the waveform, while a series of "0"s is produced in the "low" portion of the waveform.)[page]

Due to the "tracking" process of the feedback loop, the RC circuit voltage may swing around the analog input level. When the oversampling trigger changes between "1" and "0", the voltage of the RC circuit will drop from slightly above the analog input level to slightly below the analog input level. This process continues until the analog input level changes. This high frequency noise can be eliminated by using an optional digital filter.

Figure 4: Result of the conversion stage of a delta-sigma modulator.

Higher frequency designs can monitor multiple audio additional signals for operating and environmental condition communications. For example, 5k and 12K Hz signals can be sent out periodically to indicate the status of a remote audio monitoring system. These signals can indicate the environmental conditions (temperature and humidity) of the equipment. As in the previous example, multiple analog signals can be supported by simply adding more LVDS inputs. This design can serve as the center of 8 analog signals. By time-division multiplexing the inputs, only one copy of the digital logic needs to be used.

Higher frequency ADC test results

The higher frequency ADC circuit has been implemented on a Lattice XP2-17 FPGA using an evaluation board. A 15K Hz input signal with a 0V to 3.3V swing was used during testing. The analog signal was processed using the circuit of Option 2, which uses a digital filter as shown in Figure 1. The results are shown in the lower half of Figure 3, with the received signal shown in the upper window and the FFT at the bottom with the F1 frequency at 15.1K Hz. The results in the lower sidebar give the ENOB for 9 cases and a signal-to-noise ratio of 61 dB. These results show that the input signal has been successfully converted to a digital signal with good resolution and signal-to-noise ratio.