DS33Z11/DS33Z44 EEPROM Programming Guide-EEWORLD

Collect

DS33Z11/DS33Z44 EEPROM Programming Guide

Abstract: Dallas Semiconductor's Ethernet Link and Transport Processor (ELITE) product line builds a bridge between wide area networks (WANs) and local area networks (LANs). ELITE has several configuration methods, the most common of which is through microprocessor (µP) control. In addition, to reduce costs, the chip also provides hardware configuration mode or external EEPROM configuration mode. For the hardware configuration mode, due to the limited number of chip pins, the configuration of some functions will be restricted; while the EEPROM configuration mode, each register of the chip can be configured, and the function configuration is not restricted. This application note focuses on the EEPROM configuration mode of the DS33Z11 or DS33Z44 and describes how to write their EEPROM configuration software.

SPI™ Serial EEPROM Interface

The DS33Z11/DS33Z44 has a 4-wire SPI serial interface, so an external serial EEPROM can be used to initialize and configure it. By correctly setting the operating mode control pins (HWMODE = 0, MODEC1 = 1, MODEC0 = 0), the DS33Z11/DS33Z44 can act as a SPI master and read configuration data from the serial EEPROM. MOSI (master output, slave input) and MISO (master input, slave output) are data lines, SPICK is the clock line, and /SPI_CS is the chip select line to control access to the EEPROM. The CKPHA pin is used to configure the sampling and update edges of the MISO and MOSI signals. MOSI data can be output on the rising or falling edge of SPICK. MISO data can be sampled on the rising or falling edge of SPICK. The SPICK operating frequency is 8.33MHz, which is obtained by dividing the external 100MHz SYSCLKI.

SPI EEPROM Programming Steps

Because the DS33Z11/DS33Z44 uses a fixed-mode SPI memory read instruction, the EEPROM used with the DS33Z11/DS33Z44 must be a 16kB (2048 x 8) SPI serial EEPROM. SPI serial EEPROMs smaller than 16kB require a different memory read instruction, and the two instructions are incompatible. The read sequence is initiated after the initial power-on reset or after the rising edge of the /RST pin trigger signal. The SPI_/CS signal is pulled low, and the 0b00000011 SPI read instruction is issued from the data line MOSI to initiate a DS33Z11/DS33Z44 memory read operation. This is followed by a 16-bit binary address of 0x0000, and then data can be read from the data line MISO. SPI_/CS is kept low until all data is read and latched into the DS33Z11/DS33Z44. The length of the data read from the EEPROM depends on whether the DS33Z11 or DS33Z44 is connected to the EEPROM. Figure 1 shows the timing diagram for the DS33Z11/DS33Z44 to read data from the EEPROM. Table 1 shows the memory map for the DS33Z11 and Table 2 shows the memory map for the DS33Z44.

Figure 1. SPI master timing diagram

Figure 1. SPI Master Timing

Chart 1. DS33Z11 EEPROM Program Memory Map

Functional Block Address	Address Range for EEPROM Data (Hexadecimal)
Global registers	000 to 03F
Arbiter registers	040 to 07F
BERT registers	080 to 0BF
Serial interface Tx registers	0C0 to 0FF
Serial interface Rx registers	100 to 13F
Ethernet interface registers	140 to 17F
MAC register write 1 (MAC control)	180 to 186 (7-byte record for MAC indirect write)
MAC register write 2 (MII data)	187 to 18D (7-byte record for MAC indirect write)
MAC register write 3 (MII address)	18E to 194 (7-byte record for MAC indirect write)
MAC register write 4 (flow control)	195 to 19B (7-byte record for MAC indirect write)

Table 2. DS33Z44 EEPROM Program Memory Map

Functional Block Address	Address Range for EEPROM Data (Hexadecimal)
Global registers	000 to 03F
Arbiter registers	040 to 07F
BERT registers	080 to 0BF
Serial interface 1 Tx registers	0C0 to 0FF
Serial interface 1 Rx registers	100 to 13F
Ethernet interface 1 registers	140 to 17F
Serial interface 2 Tx registers	180 to 1BF
Serial interface 2 Rx registers	1C0 to 1FF
Ethernet interface 2 registers	200 to 23F
Serial interface 3 Tx registers	240 to 27F
Serial interface 3 Rx registers	280 to 2BF
Ethernet interface 3 registers	2C0 to 2FF
Serial interface 4 Tx registers	300 to 33F
Serial interface 4 Rx registers	340 to 37F
Ethernet interface 4 registers	380 to 3BF
MAC 1 register write 1 (MAC control)	3C0 to 3C6 (7-byte record for MAC indirect write)
MAC 1 register write 2 (MII data)	3C7 to 3CD (7-byte record for MAC indirect write)
MAC 1 register write 3 (MII address)	3CE to 3D4 (7-byte record for MAC indirect write)
MAC 1 register write 4 (flow control)	3D5 to 3DB (7-byte record for MAC indirect write)
MAC 2 register write 1 (MAC control)	3DC to 3E2 (7-byte record for MAC indirect write)
MAC 2 register write 4 (flow control)	3E3 to 3E9 (7-byte record for MAC indirect write)
MAC 3 register write 1 (MAC control)	3EA to 3F0 (7-byte record for MAC indirect write)
MAC 3 register write 4 (flow control)	3F1 to 3F6 (7-byte record for MAC indirect write)
MAC 4 register write 1 (MAC control)	3F7 to 3FD (7-byte record for MAC indirect write)
MAC 4 register write 4 (flow control)	3FE to 404 (7-byte record for MAC indirect write)

The Ethernet MAC registers are indirectly addressed and require multiple write instructions when configured using the µP parallel bus mode. Because these indirectly addressed registers cannot be directly mapped to the EEPROM memory, a special programming procedure is required to achieve the write operation when using the SPI serial EEPROM mode. Write operations to the indirectly addressed MAC registers use a 7-byte record that is placed at the end of the EEPROM memory. Four MAC registers (SU.MACCR, SU.MACMIID, SU.MACMIIA, and SU.MACFCR) can be configured in EEPROM mode. The remaining indirectly addressed MAC registers do not require configuration because they are the MAC status or status configuration registers and do not require initialization. The

7-byte record is based on the µP write procedure to the indirectly addressed MAC registers. The first four bytes in the record contain the 32-bit data that will be written to the Ethernet MAC Data 0 to Data 3 registers (SU.MACWD0 to SU.MACWD3). The next two bytes in the record contain the 16-bit address that will be written to the Ethernet MAC low-byte and high-byte address registers (SU.MACAWL to SU.MACAWH). Finally, the remaining bytes are written to the Ethernet MAC's Read/Write Command Status Register (SU.MACRWC), which triggers the write of the data to the actual specified address. The DS33Z44 has a different number of indirect write registers. The DS33Z44's first Ethernet interface has four indirect write registers, the same as the DS33Z11, while the remaining three interfaces have only two indirect write registers each. The reason is that there is only one MDIO port to manage the external PHY, which is controlled by MAC 1. Therefore, SU.MACMIID and SU.MACMIIA are the only valid MAC 1 registers. In order to control multiple external PHYs through the MAC 1 MDIO port, all PHY MDIO ports must be connected together and configured to the same external address.

Table 3 shows an example of writing 0x1018000C to the Ethernet MAC Control Register (SU.MACCR) with an indirect address of 0x0000. If you need support for SPI serial EEPROM programming for the DS33Z11/DS33Z44, you can find it through the links in the subsequent references section.

Table 3. DS33Z11 indirect write instruction examples

EEPROM 7-Byte Record	EEPROM Address Base from Table 1 (Hexadecimal)	EEPROM Address (Hexadecimal)	MAC Register Write 1 Used to Initialize SU.MACCR (Hexadecimal)
MAC data byte 1	Base + 00	180	0C - written to SU.MACWD0
MAC data byte 2	Base + 01	181	00 - written to SU.MACWD1
MAC data byte 3	Base + 02	182	18 - written to SU.MACWD2
MAC data byte 4	Base + 03	183	10 - written to SU.MACWD3
MAC address low	Base + 04	184	00 - written to SU.MACAWL
MAC address high	Base + 05	185	00 - written to SU.MACAWH
MAC write command	Base + 06	186	01 - written to SU.MACRWC

References

For technical support on LAN to WAN bridging designs, please contact the Telecom Product Line Technical Support Group by emailing telecom.support@dalsemi.com telecom.support@dalsemi.com(English only), or calling 972-371-6555 (USA).

Keywords：DS33Z11 DS33Z44 EEPROM Programming Reference address：DS33Z11/DS33Z44 EEPROM Programming Guide

Previous article：Technical requirements for variable frequency power supply
Next article：Multifunctional inverter and rectifier circuit in power electronics technology

Recommended ReadingLatest update time:2024-11-23 10:54

STC C51 MCU EEPROM

1. STC series microcontrollers all have built-in EEPROM units, and the operation mode of the EEPROM unit is similar to that of NOR FLASH, with the Sector unit for erasing and writing. At the same time, when rewriting the Flash data, the internal EEPROM data is not affected. This is different from the EEPROM operat

[Microcontroller]

AVR EEPROM Experiment

System functions Write data to the EEPROM inside the AVR, then read the data from the EEPROM, use LED to indicate, and observe whether the read data is consistent with the written data. hardware design AVR main control circuit schematic diagram LED control circuit schematic diagram

[Microcontroller]

The road to learning MCU for beginners (Twenty-six) --- Understanding EEPROM-IIC bus (I)

Objective: Understanding EEPROM-IIC bus (I) 1. Introduction to IIC bus IIC (Inter-Integrated Circuit) bus is a two-wire serial bus developed by PHILIPS, which is used to connect microcontrollers and their peripherals. It is a bus standard widely used in the field of microelectronic communication control. It is a spe

[Microcontroller]

The road to learning MCU for beginners (Twenty-six) --- Understanding EEPROM-IIC bus (I)

ATMEGA16 drives internal EEPROM program

// 8MHZ crystal running on ATMEGA16 // Display effect: Display the number set by the button #include iom16v.h #include macros.h #define uchar unsigned char #define uint unsigned int #pragma data:code const uchar table ="I LIKE AVR !"; const uchar table1 ="WWW*FUMANCHE*COM"; const uchar table_num

[Microcontroller]

51 MCU——EEPROM

24C02: 256-byte EEPROM. Generally, EEPROM has a lifespan of 300,000 to 1 million times. Devices based on the I2C communication protocol. I2C is a communication protocol with strict communication timing logic requirements, while EEPROM is a device that only samples the interface of the I2C protocol and is connected to

[Microcontroller]

AT93C46/56/55 Serial EEPROM and MCU Program

16-bit single-chip microcomputers have occupied a certain market in the field of industrial control due to their advantages such as being suitable for high-speed control occasions and having multiple functions. Since EEPROM can modify the contents of its storage unit without leaving the system, its application in 16

[Microcontroller]

AT93C46/56/55 Serial EEPROM and MCU Program

Reading and writing of EEPROM inside STM32 microcontroller

The STM32L series MCU provides an EEPROM storage area, but in fact, its FLASH is also an EEPROM type, but there is an area that is opened up for EEPROM operation. The STM32L EEPROM service life is designed to be more than 100,000 erase and write times, and the capacity is 2K-4K, which is ideal for parameter storage of

[Microcontroller]

Popular Resources
Popular amplifiers