Objective: Understanding EEPROM-IIC bus (I)
1. Introduction to IIC bus
IIC (Inter-Integrated Circuit) bus is a two-wire serial bus developed by PHILIPS, which is used to connect microcontrollers and their peripherals. It is a bus standard widely used in the field of microelectronic communication control. It is a special form of synchronous communication, with the advantages of few interface lines, simple control method, small device package form, and high communication rate. I2C bus has only two bidirectional signal lines. One is the data line SDA, and the other is the clock line SCL. Due to its few pins, simple hardware implementation, and strong scalability, it is widely used in major integrated chips.
I2C is a communication protocol that has strict communication timing logic requirements, while EEPROM is a device that only samples the interface of the I2C protocol and is connected to the microcontroller. There is no necessary connection between the two. EEPROM can use other interfaces and I2C can also be used in many other devices.
1.1 IIC physical layer
Common connection methods for I2C communication devices:
IIC Physical Layer
The power supply of the microcontroller (pin 40) is connected to SDA and SCL, otherwise there will be no high or low level changes.
Features:
(1) It is a bus that supports multiple devices.
(2) The I2C bus only uses two bus lines, SDA and SCL.
(3) Each device connected to the bus has an independent address, and the host can use this address to access different devices.
(4) The bus is connected to the power supply through a pull-up resistor. When the I2C device is idle, it will output a high-impedance state. When all devices are idle and output a high-impedance state, the pull-up resistor pulls the bus to a high level.
(5) When multiple hosts use the bus at the same time, in order to prevent data conflicts, arbitration will be used to decide which device occupies the bus.
(6) There are three transmission modes: the standard mode has a transmission rate of 100kbit/s, the fast mode is 400kbit/s, and the high-speed mode can reach 3.4Mbit/s, but most I2C devices currently do not support the high-speed mode.
(7) The number of ICs connected to the same bus is limited by the maximum capacitance of the bus, which is 400pF.
1.2 IIC protocol layer
The I2C protocol defines the communication start and stop signals, data validity, response, arbitration, clock synchronization and address broadcast.
(1) Data validity regulations
picture2.png
The data line is required to be high level when the clock line is high level to keep the data stable for transmission. As long as the clock line is low level, the data is allowed to change.
Each data transfer is in bytes, and the number of bytes per transfer is not limited.
(2) Start and stop signals
Start signal and stop signal
The start signal and the end signal are sent by the host and are indicated on the data line.
(3) Acknowledgement response
Acknowledgement Response
The acknowledgment response is sent by the slave after sending a byte (transmission is carried out in bytes), indicating that a byte has been sent, and then the slave can continue to receive data.
(4) Bus addressing method
I2C bus addressing can be divided into two types according to the number of bits of the slave address, one is 7 bits and the other is 10 bits. The bit definition of the 7-bit addressing byte (the addressing byte is the first byte after the start signal) is as follows:
Addressing mode
1~7 are slave address bits, which are divided into fixed addresses and programmable parts, used to adjust the number of addresses.
R/W is used to determine the relationship between the host and the slave. When R/W = 0, the host sends data to the slave. When R/W = 1, it means that the host receives data from the slave.
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