Design of FIR digital filter based on FPGA (Part 1)

In the Matlab/Simulink environment, the DSP Builder module was used to build the FIR model, and the FIR filter was designed according to the FDATool tool. Then, system-level simulation and ModelSim functional simulation were performed. The simulation results show that the filtering effect of the digital filter is good. The model was converted into VHDL language through SignalCompiler and added to the hardware design of FPGA. The real-time result waveform of the digital filter was obtained from the virtual logic analysis tool SignalTapⅡ in QuartusⅡ software, and the result was in line with expectations.

　　0 Introduction

　　In the process of information signal processing, digital filter is the most widely used method in signal processing. Through filtering operation, a set of input data sequence is transformed into another set of output data sequence, thereby realizing the change of signal properties in time domain or frequency domain. Commonly used digital filters can be divided into two types: finite impulse response (FIR) filter and infinite impulse response (IIR) filter. Among them, FIR digital filter has a strict linear phase, and the non-recursive structure also ensures the stability of operation. In applications with high real-time requirements, programmable chip FPGA is used for implementation. Compared with the implementation method of DSP chip or dedicated chip, it has the advantages of high speed, high precision and high flexibility. This paper adopts a method based on FPGA and DSP Builder to design FIR digital filter, adopts hierarchical and modular design ideas, follows the design and development process of DSP Builder, establishes a model in Matlab/Simulink and performs system-level simulation, and then performs Verilog language conversion. After ModelSim simulation verification, the real-time test of FIR digital filter is realized.

　　1 Basic principles and structure of FIR digital filter

　　For a FIR filter system, its impulse response is always finite, and its system function can be written as:

　　Where: x(n) is the input sampling sequence; h(i) is the filter coefficient; k is the filter order; y(n) represents the output sequence of the filter.

　　Figure 1 is a structural block diagram of a k-order FIR digital filter.

　　2 FIR digital filter design process

　　The design process mainly involves the development and design of tool software such as Matlab/Simulink, DSPBuilder and Quartus II. The entire design process, including system description to hardware implementation, can be completed in a complete design environment, as shown in Figure 2.

　　(1) Design input in Matlab/Simulink, that is, create a model file with the extension mdl in the Simulink environment of Matlab, and call the graphical modules (Block) in Altera DSP Builder and other Simulink libraries in a graphical way to form a system-level or algorithm-level design block diagram (or Simulink design model).

　　(2) Use Simulink's graphical simulation and analysis functions to analyze the correctness of the design model and complete model simulation, also called system-level simulation.

　　(3) A key step in DSP Builder design implementation is to convert Simulink model files into Verilog files, a universal hardware description language, through Signal-Compiler.

　　(4) The converted Verilog source code is functionally simulated using ModelSim software to verify the correctness of the Verilog file. The next few steps are to synthesize, compile and adapt the Verilog RTL code and simulation files generated by the above design in Quartus II tool software, generate a file with the extension .sof and load it into the FPGA hardware system.

　　3 Detailed Design of FIR Digital Filter

　　3.1 FIR digital filter module design and system-level simulation

　　According to the principle of FIR digital filter, a 16-order FIR digital filter structure is built in the Simulink environment, as shown in Figure 3.

　　In the process of building the model, two 8-bit Shift Taps shift register modules were used to decompose the input signal, and then the algorithm calculation was performed according to the principle of digital filter.