Research on DSP+FPGA Airborne Bus Interface Board (Part 1)

The development of ARINC429 bus interface board realizes the reception and transmission of multi-channel ARINC429 bus data, which has become the focus of the current research on aircraft airborne bus interface.

　　1 ARINC429 Bus Introduction

　　In modern civil aircraft, a large amount of information needs to be transmitted between systems and between systems and components. The ARINC specification is an industrial standard for aviation transportation developed to transmit digital data information between avionics equipment.

　　The ARINC429 (hereinafter referred to as 429) bus protocol was proposed by the U.S. Aviation Electronics Engineering Committee in July 1977, and was published and approved for use in the same year. Its full name is Digital Information Transmission System DITS. The protocol standard specifies the requirements for digital information transmission between avionics equipment and related systems. ARINC429 is widely used in advanced civil airliners, such as B-737, B-757, and B-767. Russian military aircraft also use similar technology. Our corresponding standard is HB6096-SZ-01. The ARINC429 bus has a simple structure, stable performance, and strong anti-interference. The biggest advantage is high reliability, which is due to decentralized control, reliable transmission, and good error isolation.

　　The 429 bus uses twisted shielded wires to transmit information, and transmits inversely through a pair of twisted wires, which has strong anti-interference capabilities. The modulation method uses a three-state code method of bipolar return to zero, that is, the information is modulated by a three-level state consisting of "high", "zero" and "low" states. The signal on the 429 cable and the signal after level conversion are shown in Figure 1. Each word of the 429 bus is 32 bits, and its word synchronization is based on a time interval of at least 4 bits of the transmission cycle, that is, a 4-bit code word.

　　Figure 1 429 signal and waveform after level conversion

　　2 System Overall Plan

　　The main function of the 429 bus interface board is to act as a bridge between the 429 signal and related peripherals. It can receive the bipolar return-to-zero 429 signal and convert it into a digital signal to send to the computer or other devices, and it can also convert the digital signal sent by the computer or other devices into a 429 signal output. The bus interface board introduced in this article uses FPGA and DSP to implement four 429 signal receiving channels and four 429 signal sending channels, and each channel is independent of each other. In this interface board, the time interval between every two data words is adjustable, each transceiver channel can define the word interval length separately, each channel check mode can be defined separately as odd check or even check, and data transmission can choose single frame transmission or automatic repeated transmission (repeated transmission of a certain frame).

　　The entire interface board consists of a modulation circuit, a demodulation circuit, an FPGA, a DSP, and a dual-port RAM, as shown in Figure 2.

　　Figure 2 Interface board hardware structure diagram

　　3 Hardware Circuit Design

　　3.1 Modulation and demodulation circuit design

　　After the 429 signal enters the interface board, it must first be converted into a TTL level that can be recognized by the digital circuit. Here, HOLT's HI-8482 is used to demodulate the signal and convert the standard 429 bus signal into a 5V TTL digital signal. In order to reduce interference, 39pF high-precision military capacitors are connected to the four input pins of the 429 bus signal; HOLT's HI-8585 chip is used to modulate the signal and convert the TTL digital level into a standard 429 signal.

　　3.2 FPGA internal logic design

　　According to the coding format, characteristics, transmission rules and protocol requirements of the 429 signal, an ACEX1K FPGA from ALTERA is selected to send and receive four channels of data. Each channel is divided into a receiving part and a sending part.

　　The main function of the receiving part is to convert serial data into 32-bit parallel data through serial/parallel conversion, and automatically perform error control on the received data. It can automatically detect errors such as word spacing and bit spacing errors. If there are no errors, the data will be sent to the DSP's 16-bit data bus twice for reading. The receiving module structure block diagram is shown in Figure 3.

　　Figure 3 Receiver module structure diagram