A video surveillance system solution based on DSP

　　At present, video surveillance is widely used in security monitoring, industrial monitoring, traffic monitoring and other fields. Video surveillance systems have roughly gone through three stages: first, the TV monitoring system based on analog signals, which has a single function, is easily interfered with and difficult to expand; then there is the image monitoring system based on PC, which has strong terminal functions, but is expensive and has poor stability; in recent years, with the maturity of embedded technology, embedded video acquisition and processing systems have the advantages of high reliability, fast speed, low cost, small size, low power consumption, and strong environmental adaptability.

　　Based on the above advantages of embedded systems, a DSP-based video surveillance system solution is proposed here.

　　2 System Hardware Design

　　2.1 Overall hardware structure of the system

　　The hardware design of the whole system consists of power supply, video signal processing, FPGA and peripheral interface modules. Among them, the image processing module receives the analog video signal transmitted by the CCD image sensor, and converts the analog video signal into a digital signal. The converted digital signal is processed by DSP and then converted into a digital video signal in the standard YUV 4:2:2 format. The obtained digital video signal is sent to the FPGA module to process the YUV digital signal, thereby generating a standard SVGA format with a frame rate of 60 Hz for line and field synchronization signals. Figure 1 is a block diagram of the hardware design of the system.

　　2.2 Power Module

　　The power module converts the external 12 V DC power supply into the required working voltage for each module of the system. The voltage required by the CCD image sensor is 15 V and -7 V, the voltage required by the DSP is 3.3 V and 5 V, and the voltage required by the FPGA is 1.2 V, 2.5 V and 3.3 V. This design uses the DC-DC power converter of MOTOROLA, MC34063A to convert the 12 V DC voltage into 5 V DC voltage, and the power converter TPS75003 of Texas Instruments is used to convert the 5 V direct voltage power supply into 1.2 V, 2.5 V and 3.3 V DC voltage. The working voltage of the CCD image sensor is generated by NE555 and 78L15.

　　2.3 Image processing module

　　2.3.1 Image acquisition

　　The image acquisition circuit of this design converts the analog video signal output by the CCD sensor into a discrete analog video signal, and then performs correlated double sampling and automatic gain control on the analog signal, and then transmits it to the DSP to convert it into a digital signal. Specific workflow: After the system is powered on and reset, the DSP (CXD3142) generates a control signal to drive the CCD image sensor, converts the optical signal into an analog video signal in the PAL format, and inputs the signal to the DIN and PIN pins of the CXA2096N. At this time, the input signal is correlated double sampled under the control of the SHD and SHP pins. When the falling edge of the SHD signal arrives, the DIN signal level is sampled, and when the falling edge of the SHP signal arrives, the pre-added level signal of the PIN pin is sampled again, and the two signals are sent to the automatic gain control circuit inside the CXA2096N, and output after difference operation. The output signal is then processed by black level clamping, pre-blanking, etc., and then output by the DRVOUT pin of the CXA2096N. The DSP generates the working timing of the CXA2096N.

　　2.3.2 Video signal processing (CXD3142R)

　　This design uses SONY's dedicated signal processing device CXD3142R as a signal processor. CXD3142R is a low-power, high-efficiency signal processor dedicated to processing the output signals of Ye, Cv, Mg and G complementary color single-chip CCDs; it has automatic exposure and automatic white balance functions, and can output composite video signals and YUV 8-bit digital signal outputs at the same time. It integrates a 9-bit A/D converter synchronization signal generation circuit, an external synchronization circuit and a clock control circuit. In addition, CXD3142R also has a serial communication function. Users can pre-set the register values ​​in the DSP in the PC, download them to the DSP through the serial port, and perform automatic exposure and automatic white balance on the image signal. Figure 2 is a circuit connection diagram of the video signal processing module.

　　In Figure 2, H1, H2, XV1, XV2, XV3, and XV4 are the timing drive signals of the CCD image sensor, and the EEPROM is used to store the register values ​​for DSP initialization. D0~D7 are YUV digital signals. The specific workflow is as follows: After the analog signal collected by the CCD image sensor is preprocessed by CXA2096N, the corresponding digital signal is transmitted to the DSP (CXD3142) through the VIN pin. After receiving the digital signal, the DSP uses its internal AE/AWB detection circuit, synchronization signal generation circuit, external synchronization circuit, and related algorithms to perform related processing. After the processing is completed, the 8-bit digital signal is transmitted to the FPGA module through the D0~D7 pins under the control of the line (H pin), field (V pin) signal, and clock signal (PCLK) for related processing. Through the SCK, SI, SO, and XCS pins, the CSROM, CASI, CSASO, and CASCK ​​pins communicate with the external EEPROM to realize the initialization of the DSP. In addition, the IO pin outputs the composite video signal processed by the DSP, and the image processing results are directly displayed on the CRT display through the relevant interface.

　　2.3.3 FPGA Module

　　In order to realize real-time preprocessing of digital video signal data and increase system scalability, the system design expands a Spartan3E series FPGA produced by Xilinx based on 90 nm process, whose model is XC3S250E-PQ208-4C. This FPGA has a high cost performance, and has 250,000 system gates, 5508 logic cells (LC), 612 configurable logic blocks (CLB), 216 Kbit block RAM, 12 dedicated multipliers, 158 available I/O interfaces, and 4 digital clock management units (DCM). Figure 3 is its circuit connection diagram.

　　The communication between DSP and FPGA is completed by 11 buses, including 8 data lines, line and field synchronization signals and data clock bus. Because CXD3142RDSP outputs PAL (Phase Alternation Line) digital video signals, FPGA converts this PAL video signal into VGA format. First, the YUV (4:2:2) format signal is converted into RGB (5:6:5) format, and then two SDRAMs are used as frame buffers. The interlaced to progressive conversion is completed using the interpolation algorithm between fields, and the frame rate is increased from 25 Hz to 60 Hz. At the same time, the line and field synchronization signals in SVGA format with a frame rate of 60 Hz are generated, and the amplified image data is output to the VGA interface after D/A conversion. The captured image is displayed in real time on the VGA monitor.
2.4 Peripheral interface module

　　This design supports RS-232C serial communication. However, this serial communication needs to convert the 3.3 V logic level into the RS-232C standard level. Therefore, the SP3232E series devices are used to complete the level conversion. SP3232E can generate 2Vce RS-232C voltage level from +3.0 to +5.5 V power supply voltage. This series is suitable for +3.3 V systems. The typical data rate of the SP3232E device is 235 kb/s when the driver is fully loaded. Figure 4 is the interface circuit diagram of the system design.

　　It should be noted that due to the use of SP3232E device, its driving capability is limited, so this interface circuit is only suitable for short-distance transmission. If long-distance transmission is to be carried out, the signal transmission capability must be strengthened.

　　3 System Hardware Debugging

　　System hardware debugging should first debug the power module. If the system power supply is wrong, the device will be damaged; then debug the DSP module. After the DSP is powered on, it will generally not heat up in idle state. If there is a slight heating, the power supply should be disconnected immediately to avoid damaging the DSP device. The main reason is that the working voltage of the DSP is connected to the non-voltage pin of the DSP. After the working voltage of the DSP is normal, check whether the reset circuit and the clock circuit are correct. If there is no signal on the clock pin of the DSP, it is generally a circuit solder joint. If there is a signal, but the operating frequency does not reach the normal value of the system operation, adjust the external adjustable capacitor. If it still does not meet the requirements, you should consider whether the clock signal is interfered by the low-frequency signal, and you should carefully check the circuit board and modify the wiring if necessary. The debugging of the FPGA module is the same as the above method.

　　4 Conclusion

　　The system design has been successfully applied to the digital video booth project. The product has been put into production, but the image quality needs to be improved, which may be due to the distortion of the analog video signal and the inappropriate setting of the white balance value. The design scheme has strong flexibility and can also be applied to the development of monitoring, security and other products.