Introduction to General Array Logic (GAL)

Publisher:清新时光Latest update time:2013-05-13 Keywords:Array  Logic  GAL Reading articles on mobile phones Scan QR code
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GAL is the abbreviation of many English words, which are related to electronics, physics, games and other fields, but in the electronics industry it refers to Generic Array Logic, which is one of the simple PLDs. The editor of Electronics Fans Network will take you to learn more about what GAL is, the advantages of GAL and the basic structure of GAL.

  What is GAL?

  GAL, short for generic array logic, means general array logic. GAL devices are derived from PAL. The use of EECMOS technology makes the programming of the device very convenient. In addition, because its output uses a logic macro cell structure (OLMC—Output Logic Macro Cell), the logic design of the circuit is more flexible.

  Advantages of GAL

  1. It has the function of electrical erasability, which overcomes the disadvantage of using fuse technology that can only be programmed once, and can be rewritten more than 100 times;

  2. Due to the use of output macro unit structure, users can configure according to their needs. One GAL device can realize the logical functions of the output structure of PAL devices with various configurations, which brings great convenience to circuit design;

  3. It has encryption function to protect intellectual property rights;

  4. A storage area is opened in the device to store the identification mark, which is the function of the electronic tag.

  Basic structure of GAL device

  GAL consists of five parts: input terminal, AND array part, output macro unit, system clock and output three-state control terminal.

  1. Input: GAL16V8 has 8 inputs from pins 2 to 9. Each input has a buffer, and the buffer leads to two complementary outputs to the AND array.

  2. AND array part: It consists of 8 inputs and 8 outputs, each leading to two complementary outputs, forming 32 columns, that is, the number of variables of AND terms is 16; each of the 8 outputs corresponds to an 8-input OR gate (equivalent to each output containing 8 AND terms) forming 64 rows, that is, the AND array of GAL16V8 is a 32×64 array, with a total of 2048 programmable units (or nodes);

  3. Output macro unit: GAL16V8 has 8 output macro units, corresponding to pins 12 to 19. The circuit of each macro unit can be programmed to realize the functions realized by all PAL output structures;

  4. System clock: Pin 1 of GAL16V8 is the system clock input terminal, which is connected to the clock input terminal of the D flip-flop in each output macro unit. It can be seen that the GAL device can only realize synchronous timing circuits, but cannot realize asynchronous timing circuits;

  5. Output three-state control terminal: Pin 11 of GAL16V8 is the three-state control common terminal of the device.

Keywords:Array  Logic  GAL Reference address:Introduction to General Array Logic (GAL)

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