Implementing serial communication between FPGA and PC

Introduction
Serial communication is serial data transmission. Realizing serial communication between FPGA and PC is very important in practice, especially in debugging FPGA. The debugging process generally involves software programming simulation first, and then downloading the program to the chip to verify the correctness of the design. Currently, there is no better tool that can analyze the working status and data of FPGA in real time after downloading. Through serial communication, control commands can be sent to FPGA to let it perform corresponding operations, and the required data can be sent to PC through the serial port for corresponding data processing and analysis to determine whether FPGA works according to the design requirements. This greatly facilitates the debugging of FPGA. Without the need for other additional hardware such as DSP, the debugging of FPGA can be completed only through the serial port. This paper adopts QuartusⅡ3.0 development platform and Altera's FPGA to design and implement serial communication with PC.

Figure 1 Overall block diagram

Figure 2 Send and receive flow chart

Figure 3 State machine transformation

Overall design
The main design idea is: PC sends commands to the serial port, and FPGA performs corresponding operations by judging the received control word. The overall block diagram is shown in Figure 1.
The design includes three parts: 1. Send high and low levels to the I/O port to achieve the requirements of controlling external hardware. 2. Complete the changes in the internal logic of the chip. 3. Store the required data first (generally using internal or external FIFO), and then send the data to the PC through the serial port. The PC processes and analyzes the received data. The serial port uses the standard RS-232 protocol, and the main parameters are: baud rate 28800bit/s, 8 valid bits, no parity bit, and 1 stop bit.

Implementation of each module in FPGA
Frequency division module
In the design, the 3.6864MHz clock needs to be divided by 64 to 57600 baud as the clock reference for other modules. In the specific implementation, a 6-bit counter is used, and the overflow of the counter is used as the output of the clock to achieve integer division.
Transmitting and receiving module
This module is the core part of the entire design. The design process is shown in Figure 2.
In serial communication, whether sending or receiving, there must be a clock pulse signal to locate and synchronize the transmitted data. The clock frequency used in the design is twice the baud rate (57600 bit/s). Receiving process: The initial state is the waiting state. When 0 is detected, it enters the test state. If 0 is detected again in the test state, it enters the receiving data state. After receiving 8 bits, it determines whether there is a stop bit. If there is, the receiving process ends and re-enters the waiting state. Transmitting process: The initial state is the waiting state. When the signal to start sending is received, the sending process is entered. The start bit is sent first, and then the 8-bit bit number is sent. The width of each bit is 2 cycles. When a byte is sent, a stop bit is sent. The sending ends and returns to the waiting state.
Control module
The main functions are: judging the data received from the PC and performing corresponding state transitions according to the pre-designed logic. For example: presetting a state for the port; sending the flag to start sending and the data to be sent; sending the configuration signal to the DDS to control the reading and writing of the FIFO. The state machine design in the program is shown in Figure 3.
Issues to be noted in the design
The choice of baud rate is very important for serial communication. The baud rate should not be too large so that the data will be more stable. The determination and sending of the start bit in the entire sending and receiving process is the premise of data transmission. In order to avoid the generation of bit errors, a data latch should be added to the serial input and output ports in the FPGA design.

Figure 4 Sending and receiving process

Figure 5: Control word sending process

Figure 6 The process of reading data from FIFO

Simulation results
Basic sending and receiving
As shown in Figure 4, clk is the clock signal (57600 bit/s); start_xmit is the start sending flag; sin is the serial input; datain is the parallel output; read_bit is the receiving end flag; xmit_bit is the sending end flag; sout is the serial output; dataout is the parallel output; rcv_bit is the receiving bit register. The sending and receiving module mainly completes the conversion of the serial data received from the sin port into parallel data and sends it to dataout; the conversion of the parallel data datain into serial data and serially sends it through the sout port.
Receiving: Determine whether the received serial data sin is two consecutive 0s. If so, enter the receiving process; receive 1 bit of data every two clock cycles, and receive 01101010 in sequence. If the stop bit is received, it indicates that the receiving process is over, read_bit=1. According to the serial communication protocol, data is sent in the order of low bits first and high bits later, so the actual received data is 01010110. Send: The parallel data to be sent is 01010110. When start_xmit=1, the sending is valid and the sending process begins. First, two start bits 0 are sent to ensure that the length is two clock cycles. Then 01101010 are sent in sequence, 1 bit is sent every two clock cycles, and finally the stop bit is sent. The sending process ends and xmit_bit is 1.
Send control word
In Figure 5, clk is the clock signal; a is the hexadecimal control word sent by the PC, which is the parallel output dataout in Figure 4; ma1cnt, ma2cnt, and ma3cnt are three registers; clrr is the system clear signal; ddsclr is the DDS configuration signal; fifo_clk, fifo_rd, fifo_wr, and ram_rst are the clock, read, write, and clear signals of the FIFO; start_xmit is the sending start flag; and b is the data to be sent. When receiving a is 1, fifo_wr is set to 1; when a is 18, the value of ma1cnt is sent to b. Other operations are similar, mainly the setting of ports and the control of FIFO read and write status.
Read and write data from FIFO
In Figure 6, SER_CLOCK is the system clock 3.6864MHz, sa is the divided frequency 57600bit/s; SIN is the serial input; data is the data to be output; SOUT is the serial output; fifoclk, fifowr, and fiford are the read clock, write, and read enable of FIFO. Read process: When the read enable is valid, 6 read clocks are generated first, but no data is sent to SOUT, because the first 6 cycles of FIFO are not valid data. Then a read clock is generated, and the data of FIFO is sent to data, and sent out through SOUT according to the communication protocol. After the transmission is completed, another read clock is generated to read the data of FIFO and perform the next serial output.

Conclusion
With the continuous development and widespread application of programmable devices, the communication between FPGA and peripheral devices is increasing. The implementation of serial communication introduced in this article is replicable and can be used in other occasions by simply changing the system clock frequency and control module.