How to reduce IC power consumption

Power consumption has become a critical parameter in many designs. In high-performance designs, excessive power consumption above critical temperature can impair reliability. It manifests itself as voltage drops on the chip, and can even affect timing because the on-chip logic is no longer running at ideal voltage conditions. To deal with power consumption , designers must establish power-sensitive methodologies throughout the chip design process to handle power.

Interconnect is beginning to dominate switching power, just as it dominated timing in previous process nodes. The figure on the right shows the relative impact of interconnect on total dynamic power. Today, designers have the ability to reduce power through routing optimization.

Designers can also find more opportunities for automatic power reduction during the physical design phase. Automatic power reduction during physical design will complement power reduction efforts earlier in the design process and during logic synthesis.

Power consumption is an "equal opportunity" issue: from early design trade-offs to automatic physical power optimization, all power reduction techniques complement each other and need to be considered as part of every modern design process. Engineers can apply the following guidelines as an integral part of any design methodology when solving power consumption problems. Welcome to reprint, this article comes from Electronics Fans Network (http://www.elecfans.com/)

Understand that power consumption is as important a design parameter as the performance (timing), functionality, and cost of your design. Consider power consumption when making design decisions and trade-offs. Smart design decisions early in the process can result in substantial power savings. However, it is difficult to automatically reduce power consumption in the early stages of the design process.

Use advanced design techniques to reduce power consumption, such as voltage/power island partitioning, block-level clock gating, power-down modes, efficient memory configuration, and parallelism. Advanced abstraction techniques that can reduce power consumption include dynamic voltage and frequency scaling, memory subsystem partitioning, voltage/power island partitioning, and software-driven sleep modes.

Accurately estimate power consumption at the RTL and pre-RTL levels. It is the designer's task to understand the design factors and specifications that affect overall power consumption, but advanced power estimation tools can help designers by providing them with the information they need to make appropriate trade-offs.

Explore all opportunities to automatically reduce power consumption without affecting timing or increasing area. For example, register clock gating can be used effectively during logic synthesis, but doing so may cause timing and signal integrity issues during physical design. An alternative approach is to implement clock gating during the physical design phase, when accurate timing and signal integrity information is already available.

Power savings can be achieved by optimizing interconnects during the physical design phase to reduce the capacitance of high-power nodes. Once interconnect capacitance is reduced, the logic gates that drive these lower capacitive loads can be smaller or optimized to produce lower power. Reducing leakage power using multiple threshold voltage cell replacement can also be effectively implemented at the physical level.

You shouldn't wait until tapeout to start worrying about power consumption. If you do, you may find that you have done too little, too late, to reduce power consumption.

Ignore any one power dissipation factor. For example, when you are trying to reduce switching power, leakage power may be a more important component. Excessive peak power dissipation may cause large noise spikes both inside and outside the chip.

It is believed that reducing the supply voltage or using a smaller geometry process will solve the power consumption problem. Lower supply voltage reduces the noise margin and slows down the circuit operation, which makes it difficult to achieve timing closure or even meet functional specifications. At 90nm and below, there will be greater leakage current.

Count on a "push-button" low-power solution or method. Power management must be implemented at all stages of the design process - sometimes it requires design decisions, sometimes it is more automated. Welcome to reprint, this article comes from Electronic Enthusiasts Network (http://www.elecfans.com/)

Think of power-aware design and automatic power reduction as mutually exclusive. If you combine the two in a complete power management design methodology, these two techniques will effectively help you overcome power challenges.