Design Method of N-Base Counter Based on MSI

The counter is a basic component in the digital logic system. It is the most commonly used sequential logic circuit in the digital system. Its main function is to use the different states of the counter to memorize the number of input pulses. In addition, it also has logical functions such as timing, frequency division, and calculation. The counter can not only be used to count clock pulses, but also to time, divide frequencies, generate beat pulses, and perform digital calculations. As long as it is slightly more complicated.

Using medium-scale integrated counters to design arbitrary-base counters makes design and debugging easier, and has the advantages of small size, low power consumption, and high reliability. This paper mainly explains the design idea of ​​using medium-scale integrated counters to design arbitrary-base synchronous adder counters, and discusses the design methods and steps.

2. Overview of MSI Medium Scale Counters

2.1MSI Medium Scale Counter Chip Types

There are many types of MSI medium-scale counter chips. If classified by the trigger clock method, there are synchronous counters and asynchronous counters; if classified by the "module" of the base system, there are binary counters and decimal counters; if classified by the counting method, there are adder counters, subtractor counters and reversible (add/subtract) counters; if classified by chip model, there are even more types, such as: the 74 series of 4-bit binary counter chips include 161, 163, 191, 193, 197, etc., and the decimal counter chips include 160, 162, etc.

2.2 Working Principle of MSI Medium Scale Counter

2.2.1. Take the decimal synchronous counter 74LS160 as an example

Features of 74LS160

Table 174LS160 Function Table

According to the function table, the functions of 74LSl60 are as follows:

(1) Asynchronous clear function. When CR = 0, the output Q3Q2Q1Q0 is 0000 regardless of other inputs. "×" in the table means any.

(2) Synchronous parallel setting function. LD is the preset number control terminal. Under the condition of CR=1, when LD=0, under the action of the rising edge of CP, the preset data d3d2dld0 is sent to the output terminal in parallel, that is, Q3Q2Q1Q0 is d3d2dld0 at this time.

(3) Hold function: Under the premise of CR=1 and LD=1, as long as TTTP=0, the counter will not work and the output will remain unchanged.

(4) Counting function. In normal counting, CR=1, LD=1, TTTP=1 must be set. At this time, under the action of the rising edge of CP, the counting

The counter counts the number of CPs. When the count reaches the output Q3Q2Q1Q0 of 1001, C0=1. The duration of C0=1 is from when Q3Q2Q1Q0 is 1001 to when the state of QaQ2Q1Q0 changes.

74LS161 Functions
Table 274LS161 Functions

From the function table (I), we can see that when 74LS161 is in the counting state, the terminals RD, LD, S:, S: should all be "1" (connected to a high level). If one of the T4161s is used as a low-bit counter [denoted as (1)], for this counter, each CP counts once, and it always works in the counting state.

3. Design

3.1 Using feedback zeroing method to design arbitrary base counter

For the 74LS160, which is an asynchronous reset input counter, the counter is reset to zero immediately when a valid level (low level) appears at the reset input, and is not controlled by the clock signal. For the 74LS162/74LS163, which is a synchronous reset input counter, the counter is not reset to zero immediately when a valid level (low level) appears at the reset input, and the counter must wait for the next clock signal to arrive before it can be reset to zero. The two must be distinguished when used.

3.1.1 Designing a 24-bit Counter Using Parallel Method

The circuit diagram of the 24-bit counter designed by the 74LS160 parallel zeroing method is shown in Figure 1. The working principle of this circuit: first assume that the zeroing input of the two chips is 1, then the ones-bit chip is always in the counting state because the counting control terminal ENP=ENT=1; and the ENP and ENT of the ten-bit chip are connected to the carry control terminal RCO of the ones-bit chip. Only when the counting state Q3Q2Q1Q0 of the ones-bit chip is 1001, RCO is 1. The ten-bit chip can count. If there is no feedback zeroing (that is, the MR terminal is always connected to a high level), the circuit is a 100-bit counter. Now feedback is added to the circuit. When the counting state (00100100) 8421BCD code = (24) 10, the output of the NAND gate is zero. Since the 74LS160 is asynchronous zeroing and the reset control terminal MR is valid at a low level, the counter is immediately reset to zero. Since the state (24) 10 in the circuit is fleeting, it cannot be displayed. Therefore, the circuit has 24 valid states from (00)10 to (23)10, so this circuit is a 24-base counter.

Figure 1 Design of 24-base counter using 74LS160 parallel zeroing method

In addition, if the synchronous zeroing 74LS162 counter is used to design a 24-bit counter, the feedback code must be (23) 10. The corresponding 8421BCD code is 00100011. It can be seen that the feedback signal should be taken from Q1 of the tens chip and Q1 and Q0 of the ones chip, and the corresponding NAND gate should be changed to a four-input NAND gate. The circuit diagram of the 24-bit counter designed using the 74LS162 parallel zeroing method is shown in Figure 2.

Figure 2 Design of 24-base counter using 74LS162 parallel zeroing method

The circuit diagram of the 48-base counter designed using the 74LS160 serial zeroing method is shown in Figure 3.

Figure 3 Design of 48-base counter using 74LS160 serial zeroing method

The working principle of this circuit: first assume that the zero input of the two chips is 1, then the ones-bit chip is always in the counting state because the counting control terminal ENP=ENT=1; and the tens-bit chip's ENP=ENT=1, but the counting pulse CLK of the tens-bit chip is controlled by inverting the carry control terminal RCO of the ones-bit chip. When the counting state Q3Q2Q1Q0 of the ones-bit chip is 1001, RCO is 1. When the next counting pulse arrives, RCO is 0 again. The clock pulse CLK of the 74LS160 counter is valid on the rising edge. At the same time, the ones-bit RCO changes from 1 to 0, which is equivalent to a falling edge. Through the control of the NOT gate 74LS04, a rising edge is obtained, and the tens-bit chip can count. If there is no feedback to reset to zero (that is, MR is always connected to a high level), the circuit is a 100-base counter. Feedback is added to the current circuit. When the counting state

When the state (01001000) 8421BCD code = (48) 10, the NAND gate output is zero. Since 74LS160 is asynchronously reset and the reset control terminal is valid at low level, the counter is reset to zero immediately. If the synchronous zeroing 74LS162 counter is used to design a 48-bit counter, the feedback code must be (47) 10 and the corresponding 8421BCD code is 01000111. It can be seen that the feedback signal should be taken from Q2 of the tens chip and Q2, Q1 and Q0 of the ones chip, and the corresponding NAND gate should be changed to a four-input NAND gate. The circuit diagram of the 48-bit counter designed by the 74LS162 serial zeroing method is shown in Figure 4.

Figure 4 Design of 48-base counter using 74LS162 serial zeroing method

In addition, when the serial method is used, the counting pulse CLK of the ten-bit chip can also be controlled by inverting the highest bit Q3 of the unit-bit chip through the NOT gate, and the other circuits remain unchanged. Just slightly modify Figure 3 or Figure 4.

3.2 Using feedback setting method to design arbitrary base counter

This method is applicable to some counters with preset numbers, which are realized by using the preset number control terminal LOAD. For 74LS160, which is a synchronous preset number counter, when LOAD appears to be at a valid low level and the next clock pulse signal arrives, the state of the counter output terminal Q3Q2Q1Q0=D3D2D1D0. It allows it to skip certain states to design an arbitrary base counter. Below, taking 74LS160 as an example, a 23-base counter is designed using the parallel setting method, in which the preset number terminal D3D2D1D0 can be set to zero or any four-digit binary number within ten. Then, when this circuit is set, the tens and ones of the D3D2D1D0 are set to (01100110) 8421 BCD code = (66) 10, and the tens and ones of the feedback code are (10001000) 8421 BCD code = (88) 10, which is equivalent to the decimal number 88. From this analysis, the module of the counter is (88-66) + 1 = 23, so the counter is a 23-base counter, and its design circuit diagram is shown in Figure 5. From this, we can get the design key points of the setting method: the decimal number converted from the feedback code - the decimal number converted from the code at the preset number end + 1 = the module of the designed counter. Similarly, we can also use the serial setting method to design an arbitrary base counter in the same way as the previous design.

Figure 5 Design of 23-base counter using 74LS160 parallel setting method

Since the feedback setting method is not commonly used and difficult to understand? Let's take the feedback zeroing method as an example. Through the above analysis and experience summary, we can derive the design method and steps of any N-base counter.

(1) Determine the number of counter chips required based on the counting modulus N: nn = INT (logm (N-1)) + 1, where INT represents rounding. m: When the chip is a decimal counter, m is 10; when the chip is a four-bit binary counter, m is 16.

(2) When n counter chips are connected to form a counter with a modulus of m

(3) Choose to connect n counters using either the parallel method or the serial method.

(4) Determine the feedback zeroing code. If the counter chip uses asynchronous zeroing, the feedback code is (N)10. If synchronous zeroing is used, the feedback code is (N??1)10.

(5) Conversion of feedback zero code format. If the chip is a decimal counter, convert the feedback code into 8421BCD code. If it is a four-bit binary counter, convert the feedback code into a binary number.

(6) Compare the conversion result with the status output of the counter, let the pin corresponding to 1 act on the input of the NAND gate (the low level of the feedback zeroing end is valid) or the AND gate (the high level of the feedback zeroing end is valid), and then connect the output of the NAND gate or the AND gate to the feedback zeroing end of the counter chip.