Square wave frequency multiplier (SN15844N, SN7400N)

The figure shows a square wave frequency multiplication circuit. In this circuit, gate G1 is an inverter. The input signal is inverted by G1 and then added to the input of G2. When the voltage across C1 reaches the threshold voltage of G2, the output of G2 becomes logic "0", and C2 is discharged rapidly through G2.

When the input signal returns to logic "1", C1 quickly discharges through G1, and C2 begins to charge through R2. When the voltage across C2 reaches the threshold voltage of G3, the output of G3 becomes logic "0".

NAND gates G5, G6, G7 and G8 form an XOR gate. When one of the two inputs of the XOR gate is "1" and the other is "0", its output is "1"; if the two inputs are in the same logical state, the output is "0".

Since the collector of the output stage transistor of SN15844N is open circuit, resistors need to be added between the output terminals of G1 to G4 and the power supply to form the charging circuit of C1 and C2. When selecting R1 and R2, their resistance must be lower than the input impedance of the next stage.

If the input waveform is not quite symmetrical, you can fine-tune the resistance values ​​of R1 and R2.

According to the needs, similar circuits can be added in the above circuit configuration to perform multiple frequency multiplication until a certain limit is reached. The limit is determined by the transmission delay time of G1 to G4.

With this phase shifting approach, the output pulse width varies with the input signal frequency. Within a wide range, the threshold voltage can vary the delay time by 25% or more.