Camera driver based on WINCE6.0+S3C2443

1 The role and working principle of watchdog

1.1 The role of watchdog

When an embedded control system receives external interference or system errors during operation, the program may "run away", thus paralyzing the entire system. In order to prevent this phenomenon from happening, a watchdog circuit is often added or the watchdog timer integrated in the CPU is turned on in situations where high system stability is required. The function of the watchdog is to reset the system when the system "runs away" and enters an infinite loop, allowing the system to continue running.

1.2 How watchdog works

In principle, watchdog is a timer. The timer counts the clock. When the timer overflows, a reset signal is generated to reset the entire system. The basic principle is: suppose the time for the system program to run a complete cycle is tp, the watchdog timing cycle is ti, and ti>tp. After the program runs for a cycle, the count value of the timer is modified (the watchdog timing cycle is reset) (commonly known as "feeding the dog"). As long as the program runs normally, the timer will not overflow. If the system cannot modify the count value of the timer at tp due to interference or other reasons, the timer will overflow at ti, triggering a system reset, allowing the system to run again, thereby playing a monitoring role.

2 S3C2443 watchdog

2.1 Watchdog Overview

The watchdog timer of S3C2443 is used to restore the normal operation of the controller system when the controller is disturbed by noise or system errors. It can be used as a general 16-bit timer to request interrupt service. The watchdog timer can generate a reset signal of 128 PCLK cycles.

2.2 Features of watchdog

⑴General timer mode used for interrupt requests.

⑵When the timer count value decreases to 0 (timing time is up), the reset signal of 128PCLK cycle is activated.

2.3 Structure diagram of watchdog timer

Figure 1

From the above figure, we can see that PCLK is the clock source of the watchdog timer. PCLK generates a suitable watchdog timer clock after a prescaler, and this clock is divided again by MUX. This 8-bit prescale value and frequency division coefficient are determined by the watchdog timer control register (determined by WTCON[15:8] and WTCON[4:3] respectively). The valid prescale value ranges from 0 to 28-1, and the frequency division coefficient can be 16, 32164 or 128. We can use the following equation to calculate the watchdog timer frequency and the duration of each timer clock cycle.

Figure 2

2.4 Relationship between WTDAT and WTCNT registers

Once the watchdog timer is enabled, the watchdog timer data register (WTDAT) cannot be automatically reloaded into the watchdog timer count register (WTCNT). Therefore, an initial value must be written to the watchdog timer count register before the watchdog timer starts.

Figure 3

2.5 Debugging Environment Considerations

When the S3C2443 uses the Embedded ICE (in-circuit Emulator) in debug mode, the watchdog timer cannot be operated. The watchdog timer can determine whether it is currently working in debug mode through the CPU core signal (DBGACK signal). Once the DBGACK signal of the CPU core is effective, the watchdog timer will not activate the reset output at the end of the timing, so the system cannot be reset.

2.6 Watchdog Timer Dedicated Registers

⑴Watchdog Timer Control (WTCON) Register

The WTCON register allows the user to enable or disable the watchdog timer. The user can select the clock signal from 4 different clock sources, enable or disable the middle end, and enable or disable the watchdog timer output. The watchdog timer is used to reset and restart the S3C2443 system in the event of a fault after power-on. If the controller does not want to restart, the watchdog timer can be turned off. If the user uses the watchdog timer as a normal timer, it is necessary to enable the interrupt (WTCON[2]) and disable the watchdog timer (WTCON[5]).

Figure 4

⑵Watchdog timer data (WTDAT) register

The WTDAT register is used to specify the timeout period. When the watchdog timer operation is initialized (that is, the first time it is initialized), the content of the WTDAT register cannot be automatically loaded into the watchdog timer count register (WTCNT). However, using the initial value 0x8000 can drive the first timeout. In this case, the value of the WTDAT register will be automatically reloaded into the WTCNT register.

Figure 5

⑶Watchdog timer count (WTCNT) register

The WTCNT register contains the current count value of the watchdog timer during normal operation. Note that the value of the WTDAT register cannot be automatically loaded into the WTCONT register when the watchdog timer is enabled, so we need to initialize an initial value for the WTCONT register before enabling the watchdog timer.

Figure 6

3 Initialization code in WINCE

The OEMInit function in the Init.c file calls the OALTimerInit function. The following is the code for the OALTimerInit function to initialize the watchdog.

Figure 7

The SMDKInitWatchDogTimer function is implemented in watchdog.c as follows:

Figure 8

The dog feeding function RefreshWatchdogTimer in the figure above is defined in watchdog.c, as shown in Figure 1, and pfnOEMRefreshWatchDog and dwOEMWatchDogPeriod are defined in WINCE600/public/common/oal/inc/bceoemglobal.h, as shown in the figure below:

Fig. 9

The definitions of pfnRefreshWatchDog, dwWatchDogPeriod and dwWatchDogThreadPriority in the above figure are defined in WINCE600/public/common/oal/inc/oemglobal.h as follows

Fig.10