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Playing with Zynq Serial 48——[ex67] Vivado FFT and IFFT IP core application examples [Copy link]

1 About Fourier Transform

The Fourier transform is such a magical transform, its basic principles and applications are everywhere in textbooks and on the Internet, so I will not go into details here to avoid the suspicion of filling up the word count. Next, we will use Matlab and FPGA tools to compare the data generated by Vivado 's FFT IP core.

2 Matlab generates test data and draws cosine time domain and frequency domain waveforms

Use the Matlab source code fft_1line.m in the project\zstar_ex67\matlab folder to run and generate a set of 1000 sampling point data of cosine waveform , which is stored as time_domain_cos.txt file. Each data bit in this file is 16bit wide , fixed point signed (1.15) , that is, the highest bit is the sign bit, and 15 decimal places. At the same time, draw the cosine time domain and frequency domain waveforms in Matlab as follows.

3 Add and configure FFT IP core in Vivado

In Vivado , open IP Catalog and search for FFT or find the category Core à Digital Signal Processing à Transform à FFTs to find the free IP core Fast Fourier Transform . Double-click this IP .

The first Configuration page is shown in the figure, where you can set the number of IP channels ( Number of Channels ), FFT transform length ( Transform Length ), target clock frequency ( Target Clock Frequency ) and FFT implementation architecture ( Architecture Choice ).

As shown in the figure, the second Implementation page can configure the data format ( Data Format ), scaling mode ( Scaling Options ), data end processing method ( Rounding Modes ), input data and phase width ( Input Data Width ) and data output order ( Output Ordering ), etc.

In the third Detailed Implement page, you can select and configure resources related to FPGA memory or multiplier.

On the left side of the configuration page, you can view information such as IP interface ( IP Symbol ), implementation signal width details ( Implementation Details ) and output delay ( Latency ).

4. Using FPGA IP for FFT calculation

Use Vivado 16.2 to open the project under project\zstar_ex67 . In the Sources panel, expand Simulation Sources à sim_1 and confirm that the zstar_fft_sim file is the top module (the file name is displayed in bold). If it is not the top module , you can right-click the file and click the Set as Top menu item. As shown in the figure, if the Set as Top menu item is gray and cannot be clicked, it means that the current module is already the top module . In the zstar_fft_sim file, the 1000 -point cosine data time_domain_cos.txt text generated by MATLAB is imported in the form of a test script and sent to the FFT IP core for calculation. The real and imaginary parts of the output FFT results are stored in the fft_result_real.txt and fft_result_image.txt texts respectively (the simulation test results are located in the project\zstar_ex67\zstar.sim\sim_1\behav folder).

In the Flow Navigator panel, expand Simulation , click Run Simulation , and click Run Behavioral Simulation in the pop-up menu to run the simulation.

After the simulation interface pops up, click the Run All icon to run the simulation as shown in the figure.

After the simulation is completed, you can see the FFT input data waveform and the resulting output waveform as shown in the figure.

You can open the fft_result_real.txt and fft_result_image.txt files in the project\zstar_ex67\zstar.sim\sim_1\behav folder to store the real and imaginary parts of the FFT results respectively. Here you need to pay attention to the decimal places of the fixed point. On the left side of the IP core page, click Implementation Details to see the decimal place calibration of the fixed point. The bit width definition of all 1024 input points is the same, so as shown in the figure, you only need to check the fixed point calibration information of point 0 .

For detailed FFT IP core configuration instructions, please refer to the Xilinx official document pg109-xfft.pdf .

For the fft_result_real.txt and fft_result_image.txt texts generated by simulation , you can use the Matlab script draw_wave_from_txt.m ( in the project\zstar_ex67\matlab folder) to load and draw the waveform. The FFT operation result implemented by FPGA is drawn as follows. You can compare it with the waveform of Matlab , which is almost the same. Of course, due to the limited precision of FPGA input data (precision loss from floating point to fixed point), it is impossible to be completely consistent.

5. Using FPGA IP for IFFT calculation

In the Sources panel, expand Simulation Sources à sim_1 and set the zstar_ifft_sim.v file as the top module . In the zstar_ifft_sim file, in the form of a test script, based on the FFT result generated by the zstar_fft_sim.v test script, continue to enter this result into the IFFT IP core for IFFT operation, and finally upload the IFFT result. The real part of the output IFFT result is stored in the ifft_result.txt text (the simulation test results are located in the project\zstar_ex67\zstar.sim\sim_1\behav folder). You can compare the data in this text with the time_domain_cos.txt text, which is almost the same.

The FFT result output by xfft_0 is a fixed-point signed (12.15) . To obtain the final FFT result, the result output by the IP core needs to be divided by the number of FFT data (i.e. 1024 ), so we can assume that the actual FFT result is a fixed-point signed (2.25) .

The input interface of xfft_1 for IFFT is fixed-point signed(1.26) , and the two do not match. So we think that the input data is shifted right by 1 bit, and the IFFT output should be shifted left by 1 bit. The output of IFFT is signed(12.26) , so after shifting left by 1 bit, it is signed(13.25) .


This content is originally created by EEWORLD forum user ove . If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source

This post is from FPGA/CPLD

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Hi, I encountered many problems when using the FFT core and could not generate correct data. I read your FFT core usage method and it was very good, but the timing of the code I wrote myself had problems. After inputting the data, the value of the variable s_axis_data_tlast had problems, and an extra number was output when outputting. I don't know where the problem is. Can you give me some advice?   Details Published on 2020-6-21 15:48
 

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Hi, I encountered many problems when using the FFT core and could not generate correct data. I read your FFT core usage method and it was very good, but the timing of the code I wrote myself had problems. After inputting the data, the value of the variable s_axis_data_tlast had problems, and an extra number was output when outputting. I don't know where the problem is. Can you give me some advice?

This post is from FPGA/CPLD
 
 

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