A brief discussion on STM8S_008_WDG independent watchdog and window watchdog

ⅠWritten in front

STM8S watchdog WDG is divided into two categories:

IWDG: Independent WatchDog

WWDG: Window WatchDog

The independent watchdog module can be used to solve the processor errors caused by hardware or software failures. It is driven by an internal 128kHz LSI RC oscillator as the clock source, so it still works normally even when the main clock fails.

The window watchdog is used to monitor software errors caused by external interference or unpredictable logic conditions. Such software errors usually cause the application to run in an unexpected manner.

The main meaning is: IWDG mainly prevents reset caused by hardware problems, and WWDG mainly prevents reset caused by software problems.

For your convenience, the content of this article has been organized into a PDF file:

http://pan.baidu.com/s/1i5uWhJR

Ⅱ Watchdog Knowledge

1. Watchdog structure diagram

The independent watchdog IWDG of STM8S looks simpler than the window watchdog WWDG. In fact, there are only two registers, and the software configuration is relatively simple. Whether it is an independent or window watchdog, you can basically understand them by looking at the structure diagram. Please see the structure diagram below for comparison.

Independent watchdog IWDG structure diagram:

When the down counter "8-bit down-counter" is equal to 0, the watchdog reset "WDG reset" will be generated. Therefore, it is necessary to update the counter value by reloading the register "IWDG_RLR" before the counter is equal to 0.

Window watchdog WWDG structure diagram:

There are two places where the window watchdog will cause a reset:

1. When the 7-bit (T[6:0]) down counter rolls over from 0x40 to 0x3F (T6 bit is cleared). This is similar to IWDG above, and it will reset when it decrements to "0".

2. When the updated count value is greater than the window value (T6:0 > W6:0).

The two reset situations are shown in the following figure:

2.IWDG independent watchdog function

When the value 0xCC is written to the key register (IWDG_KR), the independent watchdog is enabled and the counter starts counting down from its reset value 0xFF. When the count reaches 0x00, a reset signal (WDG RESET) is generated.

If the hardware watchdog function is enabled in the IWDG_HW selection byte, the watchdog function is automatically turned on when the chip is powered on. If the software cannot operate the key register in time, a reset is generated when the counter reaches 0x00.

The timeout value of the watchdog reset is determined by your configuration (division value and count value), which is roughly as follows (the default LSI = 128 kHz will vary with temperature):

3.WWDG independent watchdog function

● Programmable free-running down counter

● Conditional reset

─ If the watchdog is enabled, a reset occurs when the down counter value is less than 0x40

─ If the watchdog is enabled, a reset is generated when the down counter is reloaded outside the specified time window

● Hardware or software start watchdog (specified by option byte)

● A reset can be generated during HALT instruction (configured by option byte)

● Enable watchdog:

If the software watchdog is selected (by the option byte), the watchdog is disabled after a system reset. Setting the WDGA bit in the WDGCR register will enable the watchdog, which will then not be disabled until the next reset.

If the hardware watchdog is selected (via the select byte), the watchdog will always be enabled and the WDGA bit will have no effect.

● Control the down counter:

The down counter is a free-running counter: it keeps counting down even if the watchdog is not enabled. When the watchdog is enabled, the T6 bit must be set to avoid an immediate reset.

The T[5:0] bits contain the time delay allowed before the watchdog generates a reset; because the state of the prescaler is unknown when writing to the WDGCR register, this time delay is between a minimum and maximum value.

The value of the window register (WDGWR) is the high limit of the specified window: To prevent a reset, the down counter must be refreshed when the value of the down counter is less than the value of the window register and greater than 0x3F.

Tip: The T6 bit can be used to generate a software reset (i.e. set the WDGA bit and clear the T6 bit at the same time).

● Generates watchdog reset when stopped

If the watchdog is enabled and the option to generate a watchdog reset when stopped is selected, executing the HALT instruction will generate a reset.

ⅢSoftware Engineering Source Code

1. About the project

This article provides two versions of engineering code:

STM8S-A08_IWDG independent watchdog

STM8S-A08_WWDG Window Watchdog

The engineering code provided in this article is based on the previous software project "STM8S-A04_UART basic data transmission and reception" to add the WDG watchdog. Beginners can refer to my previous corresponding basic articles, which are more detailed.

2.IWDG independent watchdog code analysis

A.IWDG_Initializes

voidIWDG_Initializes(void)

{

IWDG_Enable();

IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);

IWDG_SetPrescaler(IWDG_Prescaler_256);

IWDG_SetReload(250);

IWDG_ReloadCounter();

}

The prescaler value is IWDG_Prescaler_256, and the parameter is an enumeration type:

typedef enum

{

IWDG_Prescaler_4 = (uint8_t)0x00,

IWDG_Prescaler_8 = (uint8_t)0x01,

IWDG_Prescaler_16 = (uint8_t)0x02,

IWDG_Prescaler_32 = (uint8_t)0x03,

IWDG_Prescaler_64 = (uint8_t)0x04,

IWDG_Prescaler_128 = (uint8_t)0x05,

IWDG_Prescaler_256 = (uint8_t)0x06

} IWDG_Prescaler_TypeDef;

The reload count value is an 8-bit register with a maximum value of 255, which we set to 250.

When I initialized the watchdog, I set the reset timeout value to 1000ms. The specific calculation is as follows:

128K/2 = 64K (input clock)

64K / 256 = 250 (clock after division)

250 / 250 = 1 (overload value is 250)

B. Functional test code

voidmain(void)

{

System_Initializes();

UART1_Printf((uint8_t*)"Start...");

while(1)

{

LED_REVERSE ;

TIMDelay_Nms(990);

IWDG_ReloadCounter();

}

}

First: If reset, it will print "Start...";

Second: We configure the reset timeout value to 1000ms. Theoretically, the dog will not be reset if it is fed within 1000ms. Due to the deviation of LSI, we set it to feed the dog once every 990ms.

Third: Change the delay value to 1010, and you will find that the system is reset (printing "Start...").

3.WWDG window watchdog code analysis

A.WWDG_Initializes

#define WWDG_WINDOW_VALUE 0x7F //Window value

#define WWDG_COUNTER_INIT 0x7F //Count value

voidWWDG_Initializes(void)

{

WWDG_Init(WWDG_COUNTER_INIT, WWDG_WINDOW_VALUE);

}

To facilitate testing, we define the window value and count value as macros, ranging from 0x40 to 0x7F.

B. Functional test code

voidmain(void)

{

System_Initializes();

UART1_Printf((uint8_t*)"Start...");

WWDG_Initializes();

while(1)

{

LED_REVERSE;

TIMDelay_Nms(49);

WWDG_SetCounter(WWDG_COUNTER_INIT);

}

}

First: Similarly, if reset, it will print "Start...";

Second: We configure the reset timeout value to 49.152ms. If this delay is greater than 49 (set to 50 and above), it will reset (print "Start...").

Third: If we modify the delay value (for example, TIMDelay_Nms(10);), and modify the window value to #define WWDG_WINDOW_VALUE 0x4F, it will not be within the dog feeding window range, and the system will be reset (printing "Start...").

Reminder: More testing and verification will make it easier to understand and remember the key points of the function.

IV Download

STM8S information:

http://pan.baidu.com/s/1o7Tb9Yq

Two versions of software source code project (STM8S-A08_xWDGxx watchdog):

http://pan.baidu.com/s/1c2EcRo0