Summarize the commonly used communication interfaces of microcontrollers
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In embedded systems, on-board communication interfaces refer to the communication paths or buses used to connect various integrated circuits to other peripheral devices. The following are commonly used on-board communication interfaces: including I2C, SPI, UART, 1-Wire:
I2C Bus
The I2C bus is a synchronous, bidirectional, half-duplex, two-wire serial interface bus. Here, half-duplex means that at any given moment, only one direction can communicate.
The I2C bus was first developed and marketed by Philips Semiconductor in the 1980s. The original design goal of I2C was to provide a simple method for connecting microprocessor/microcontroller systems with TV peripheral chips.
The I2C bus consists of two bus lines: the serial clock line SCL and the serial data line SDA.
SCL line - responsible for generating synchronous clock pulses.
SDA line - responsible for transmitting serial data between devices.
The I2C bus is a shared bus system, so multiple I2C devices can be connected to the system. Devices connected to the I2C bus can act as either a master device or a slave device.
The master device is responsible for controlling the communication by initializing/terminating the data transfer, sending the data and generating the required synchronization clock pulses.
The slave device waits for commands from the master device and responds to command reception. Both the master device and the slave device can act as a sending device or a receiving device. Regardless of whether the master device acts as a sending device or a receiving device, the synchronous clock signal can only be generated by the master device.
I2C supports the simultaneous existence of multiple master devices on the same bus. Figure 1-1 shows the connection relationship between the master device and the slave device on the I2C bus.
When the bus is idle, SDA and SCL are both in a high level state. When the host wants to communicate with a slave, it will first send a start condition, then send the slave address and read/write control bit, and then transmit data (the host sends or receives data). When the data transmission is completed, the host will send a stop condition. Each byte transmitted is 8 bits, with the high bit first and the low bit last.
· Start condition: When SCL is high, the host pulls SDA low, indicating that data transmission is about to begin.
· Slave address: The first byte sent by the host is the slave address. The high 7 bits are the address, and the lowest bit is the R/W read/write control bit. 1 indicates a read operation, and 0 indicates a write operation.
Generally, there are two types of slave addresses: 7-bit address mode and 10-bit address mode. If it is 10-bit address mode, the first 7 bits of the first byte are a combination of 11110XX, where the last two bits (XX) are the two highest bits of the 10-bit address, and the second byte is the remaining 8 bits of the 10-bit slave address, as shown in the following figure:
· Acknowledge signal: After each byte of data is transmitted, the receiver needs to reply with an ACK (acknowledge). The slave sends ACK when writing data, and the host sends ACK when reading data. When the host reads the last byte of data, it can send NACK (Not acknowledge) followed by a stop condition.
· Data: After the slave address is sent, some instructions may be sent, depending on the slave, and then data transmission begins. It is sent by the master or slave. Each data is 8 bits, and there is no limit on the number of bytes of data.
Repeated start condition: During a communication process, the host may need to transfer data with different slaves or need to switch read and write operations. In this case, the host can send another start condition.
· Stop condition: When SDA is at a low level, the host pulls SCL high and keeps it at a high level, and then pulls SDA high, indicating the end of the transmission.
SPI Bus
The SPI bus is a synchronous, bidirectional, full-duplex 4-wire serial interface bus, first proposed by Motorola. SPI is a system consisting of "single master device + multiple slave devices". It should be noted that in the system, as long as only one master device is active at any time, there can be multiple SPI master devices. It is often used to achieve communication between EEPROM, FLASH, real-time clock, AD converter, digital signal processor and digital signal decoder.
In order to achieve communication, SPI has 4 signal lines, namely:
(1) Master Out Slave In (MOSI): The signal line that transmits data from the master device to the slave device, also known as Slave Input/Slave Data In (SI/SDI).
(2) Master In Slave Out (MISO): The signal line that transmits data from the slave device to the master device, also called slave output (Slave Output/Slave Data Out, SO/SDO).
(3) Serial Clock (SCLK): The signal line that transmits the clock signal.
(4) Slave Select (SS): Signal line used to select slave devices, low level is valid.
How to use SPI:
The chip shown in the figure above has two SPI controllers. The SPI controller corresponds to the SPI master device, and each SPI controller can connect multiple SPI slave devices. The slave devices mounted on the same SPI controller share three signal pins: SCK, MISO, and MOSI, but the CS pin of each slave device is independent.
The master device selects the slave device by controlling the CS pin, which is generally valid at low level. At any time, only one CS pin on an SPI master device is in a valid state, and the slave device connected to the valid CS pin can communicate with the master device at this time.
Therefore, the SPI communication method can use a "one master and multiple slaves" structure for communication. Each device connected to the bus has a unique address. The master device starts data transmission and generates a clock signal. The slave device is addressed by the master device. Only one master device is allowed at the same time.
The clock of the slave device is provided by the master device through SCLK, and MOSI and MISO complete data transmission based on this pulse. The working timing mode of SPI is determined by the phase relationship between CPOL (Clock Polarity) and CPHA (Clock Phase). CPOL indicates the initial level of the clock signal. CPOL is 0, which means that the initial state of the clock signal is low level, and 1 means that the initial level of the clock signal is high level. CPHA indicates which clock edge the data is sampled at. CPHA is 0, which means that the data is sampled at the first clock change edge, and CPHA is 1, which means that the data is sampled at the second clock change edge.
There are 4 working timing modes according to different combinations of CPOL and CPHA: CPOL=0, CPHA=0, CPOL=0, CPHA=1, CPOL=1, CPHA=0, CPOL=1, CPHA=1
UART
UART——Universal Asynchronous Receiver/Transmitter. As a type of asynchronous serial communication protocol, UART works by transmitting each character of the transmitted data one bit at a time. It is a data bus that is used more frequently during application development.
UART-based data transmission is an asynchronous form of serial data transmission. UART-based serial data transmission does not require the use of a clock signal to synchronize the transmitting and receiving ends of the transmission, but relies on a predefined configuration between the transmitting device and the receiving device.
For both the sending device and the receiving device, the serial communication configuration (baud rate, number of bits per word, parity, start bit and end bit, flow control) should be set to be exactly the same. By inserting a specific bit sequence into the data stream, the start and end of the communication can be indicated. When sending a byte of data, a start bit needs to be added at the beginning of the bit stream and an end bit needs to be added at the end of the bit stream. The least significant bit of the data byte is immediately after the start bit.
The characteristic of the UART serial port is that it transmits data one bit at a time. Two-way communication can be achieved with just two transmission lines. One line sends data while the other line receives data.
There are several important parameters for UART serial communication, namely baud rate, start bit, data bit, stop bit and parity bit. For two ports using UART serial communication, these parameters must match, otherwise the communication will fail.
Start bit: indicates the beginning of data transmission, the level logic is "0".
Data bit: Possible values are 5, 6, 7, 8, and 9, indicating the transmission of these bits of data. The general value is 8, because an ASCII character has 8 bits.
Parity bit : It is used by the receiver to check the received data and check whether the number of "1" bits is even (even parity) or odd (odd parity) to verify the correctness of data transmission. This bit is not required when using it.
Stop bit: indicates the end of a frame of data. The level logic is "1".
Baud rate: The speed of serial communication, which is expressed by the number of effective bits (bits) of binary code transmitted per unit time, and its unit is bits per second (bps). Common baud rate values include 4800, 9600, 14400, 38400, 115200, etc. The larger the value, the faster the data transmission. A baud rate of 115200 means that 115200 bits of data are transmitted per second.
1-Wire Interface
The 1-Wire interface is an asynchronous half-duplex communication protocol developed by Maxim Dallas Semiconductor (homepage: http://www.maxim-ic.com), also known as the Dallas 1-Wire protocol. In it, according to the master-slave communication model, only a single signal line DQ is used to achieve communication.
An important feature of the 1-Wire bus is that it allows power to be transferred over the signal line. The 1-Wire interface supports a single master device and one or more slave devices connected to the bus.
Parallel interface
On-board parallel interfaces are usually used for communication between the system and peripheral devices, where the peripheral devices are memory mapped to the main control side of the system. As long as the main control processor/controller of the embedded system has a parallel bus, devices that support the parallel bus can be directly connected to the bus system. There is a control signal interface between the peripheral device and the main control side to control the data communication on the parallel bus. Here, the control signals for communication include read/write signals and device selection signals. Generally speaking, the peripheral device has a device selection line; the device is only valid when the main control processor selects this line.
The direction of data transfer can be from the host to the peripheral device or from the peripheral device to the host; this is controlled by the read and write control signal lines. Only the host processor can control the read control signal and the write control signal. Generally speaking, the peripheral device is mapped to the host processor through memory, so that it can access the assigned address range. At this time, the device needs to use address decoding circuits to generate chip select signals.
When the address selected by the processor is within the specified range of the device, the decoder circuit triggers the chip select line to activate the device. The processor can then enable the corresponding control lines ( RD\ and WD\, respectively) to read data from the device or write data to the device.
In order to achieve parallel communication, the system needs to strictly follow the timing specifications. As mentioned earlier, parallel communication is initiated by the master processor. If a peripheral device wants to initialize the communication, it can send an interrupt to the processor to inform the relevant information. In order to achieve the above functions, the interrupt line of the device needs to be connected to the interrupt line of the processor, and the master processor needs to trigger the corresponding interrupt. It should be noted that the data bus width of the master processor determines the width of the parallel interface, which can be 4 bits, 8 bits, 16 bits, 32 bits, 64 bits, etc. The bus width supported by the device should be exactly the same as the master processor.
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