Unique clock design of MSP430x4xx series microcontrollers

The design of the microcontroller clock system is critical to the overall performance of the system. In order to obtain a cheap, accurate and stable clock, in most cases, a quartz crystal or a ceramic oscillator can be used as a reference clock. The typical operating frequency range of these devices is 100kHz to 10MHz. However, they all have some disadvantages, namely that the current consumed by the oscillator increases with the increase of the oscillation frequency of the oscillator. Therefore, if the quartz crystal oscillator used has a high Q value, then after the system is powered on, it will take a long time for the frequency and amplitude to reach a steady state, so the quartz crystal oscillator cannot provide a fast response to interrupts.

For a battery-powered system, the most basic requirement is low power consumption. However, there are some conflicting issues, because although the use of low-frequency clocks can achieve energy saving and extend battery life, the use of high-frequency clocks can achieve rapid response to events and enhance the ability to handle emergencies; in addition, in some cases, the clock is also required to have a high degree of stability.

Since the MSP430x4xx series microcontrollers use an enhanced frequency-locked loop FLL+ (Frequency-Locked Loop Plus) to provide the system clock, the above contradictions can be better resolved, thereby further optimizing the system cost, power consumption, processing power and stability.

1 Introduction to MSP430 Microcontroller

The MSP430 series is a 16-bit ultra-low power microcontroller launched by Texas Instruments (TI) in the United States. This series of microcontrollers has the advantages of strong processing power, fast running speed, simple instructions, low power consumption, etc., and has flexible and simple peripherals. Due to the use of many advanced technologies such as JTAG technology, FLASH online programming technology, BOOTSTRAP, etc., it has a high cost performance. The MSP430 series devices are powered by a 3V power supply and have an operating frequency of 1MHz. The speed of its single-cycle 16-bit instructions can reach 1MIPS (million instructions per second) and the current consumption is only 400μA. In fact, it only takes 6μs for the MSP430 to go from low-power mode 3 (current consumption is only 1.5μA) to a fully activated state, so it can handle interrupts in real time very well. These superior features of the MSP430 are mainly derived from its two-sided design, namely the 16-bit reduced instruction architecture and the unique clock system.

The clock system of the MSP430x4xx series products uses FLL instead of the traditional PLL (Phase-Locked Loop) design. This is mainly because FLL can start quickly and reach stability. It takes hundreds or even thousands of clock cycles for PLL to reach the locked state, while FLL+ can be locked immediately when the system starts after being accurately set in advance, thus providing a guarantee for rapid response to interrupts. In addition, PLL is usually implemented with analog components, so it needs to consume energy continuously. FLL is a pure digital system that can be controlled by software. In the inactive mode, its current consumption is 0.

2 Composition of FLL＋ module

The FLL+ clock module of the MSP430x4xx series is an extension of the FLL structure of the MSP430x3xx series, but it is very different from the clock system of the MSP430x1xx series, which does not have a hardware FLL. Therefore, in order to obtain a more accurate clock, the DCO frequency calibration must be performed by software, which is the so-called "soft frequency locking". Since the frequency range supported by FLL+ is larger, a watch crystal or a high-frequency crystal can be used. Figure 1 shows the basic composition of the FLL+ module. It can be seen from the figure that: FLL+ is mainly composed of LFXT1 oscillator, LFXT2 oscillator, DCO oscillator, frequency-locked loop, and clock buffer output.

2.1 LFXT1 Oscillator

The signal generated by LFXT1 is called ACLK. By configuring the associated registers and connecting different crystals or resonators, LFXT1 can operate in two modes: low frequency or high frequency mode. The low frequency usually uses a 32768Hz watch crystal, and the high frequency range is 455kHz to 8MHz. In most cases, LFXT1 runs in low frequency mode for the following reasons:

(1) Low operating frequency and low power consumption. When entering low power mode 3, only the watch crystal is active. The typical current consumption is only 1.5μA.
(2) High stability.
(3) Low price.
(4) Small size.
(5) Simple circuit. No external capacitor is required when connected to a watch crystal.

Since the power consumption of the watch crystal is very small, it can work continuously, thus avoiding the delay required for startup and stabilization. And the 32768Hz clock is always valid, which also means that some on-chip peripherals of the system can continue to be active when other systems are shut down. For example, the LCD or a timer used as a real-time clock can be active.

If necessary, LFXT1 can also work in high frequency mode by connecting an external high-speed crystal or resonator, but an external capacitor is required.

2.2 LFXT2 Oscillator

LFXT2 is a high-frequency oscillator, and its operating frequency is also 455kHz~8MHz. LFXT2 has a relatively simple structure. If the system needs a high-frequency clock with high stability, it can be used. If it is not needed, it can be turned off by software. However, the two pins of the high-frequency oscillator must be connected to external capacitors.

2.3 DCO Oscillator and Frequency Locked Loop (FLL)

The DCO (Digitally-Controlled Oscillator) oscillator of the MSP430x4xx series FLL+ module is an integrated RC oscillator. The generated clock signal is called DCOCLK, which can be used as the system clock (MCLK) and the clock (SMCLK) of peripheral devices after FLL adjustment and calibration. This module is the core of the entire clock system. Its basic structure is shown in Figure 2.

2.4 Clock buffer output

Since the MSP430 provides a clock buffer output (see Figure 1), its frequency division ratio FLL DIV can be controlled by software programming to divide ACLK by 1, 2, 4, 8, etc. The divided output can be used to provide clocks for peripheral circuits.

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3 Working Principle of FLL＋

For RC oscillators, since their frequency varies with temperature and voltage, when high clock accuracy is required, DCOCLK usually needs to be calibrated through FLL before it can be used as the system clock.

3.1 Frequency doubling scheme

When a higher data processing speed is required, ACLK cannot handle the task alone. In this case, frequency multiplication technology is used. In order to support a wider range of frequency changes, the FLL+ frequency multiplication scheme adds a DCO+ control bit. When DCO+ is 0 or 1, the fDCOCLK output clock frequency is different, as follows:

The programmable factor N ranges from 1 to 127, and D is 1, 2, 4, or 8. Therefore, when DCO＋＝1, N＝127, and D＝8, the output frequency of DCO is the maximum. Its value is:

In the formula, fACLK is 32768Hz. It can be seen that by changing N, D and DCO+, the DCO frequency used as MCLK/SMCLK can be easily adjusted. However, it should be noted that the final MCLK cannot exceed the operating frequency of the device.

3.2 Frequency tap

The output clock of the DCO is DCOCLK, which is divided by (D×(N+1)) and compared with ACLK. If DCOCLK is used for the system clock MCLK, the synchronizer will compare ACLK with MCLK/(D×(N+1)), and then use the difference to count the "up" or "down" mode of a 10-bit frequency synthesizer. In this way, MCLK/SMCLK can be continuously adjusted on 1024 possible settings. Once the frequency is locked, the error signal output by the synchronizer becomes 0, and MCLK = N×ACLK. In the 10-bit output of the frequency synthesizer, 5 bits are used for DCO frequency taps (NDCO) and the other 5 bits are used for frequency adjustment (NDCOMOD). 5 taps can form 29 frequencies (28, 29, 30 and 31 taps are the same), and each tap is about 10% higher than the previous one.

It is obvious that DCO can only generate some discrete frequency components. Therefore, it is impossible to make the output of the synchronizer reach strict 0 by simply changing N, D and DCO+.

3.3 Frequency adjustment

The function of the DCO frequency adjuster is to reduce the long-term cumulative cycle variation by mixing adjacent DCO cycles. In other words, it is to reduce the error between the output frequency and the required frequency by controlling the ratio of fn+1 in one adjustment cycle. The specific frequency adjuster jump mode is shown in Figure 3. In the figure, the adjuster takes 32 DCO clock cycles as one cycle. NDCOMOD can be used to define the proportional constant of fn+1 that needs to be mixed.

The following formula defines the relationship between the DCO long-term output frequency and the adjacent hopping frequency:

It can be seen that the frequency adjuster adjusts the output frequency of the DCO by independently selecting fn or fn+1 for each DCO cycle, thereby achieving the purpose of fractional tapping.

It must be clear that the accuracy of MCLK is only based on the average. For short-term accuracy, since each cycle comes from the adjacent DCO frequency tap, it is inaccurate; for long-term accuracy, the relative error is reduced due to the cumulative average. In fact, since the cycle of the adjuster is 32 and the adjustment amount is 10% of each frequency segment each time, the relative error can be reduced to less than 0.33%.

The output frequency of the DCO can also be determined by software programming NDCOMOD, so as to achieve the purpose of fast locking when using FLL frequency locking; and when not using FLL, no external crystal oscillator is required to generate the required frequency. If the required frequency f is 100Hz, and it is assumed that the frequency of the DCO at 0 tap is f0 = 700Hz. Then the two frequencies adjacent to f are:

Substituting these two frequencies into the above formula, we can get NDCOOD = 24. Therefore, if the DCO center frequency is 1MHz, then, by writing 24 into the register corresponding to NDCOMOD, the required clock can be obtained without an external crystal oscillator. In this application condition, it is necessary to pay attention to the following points:

●FLL and the regulator are enabled by default when the system is reset. To work in this state, the FLL must be disabled first. Otherwise, the DCO will automatically lock to f0;
●f0 is uncertain. In specific applications, it should be measured first and then used to calculate the required adjacent frequencies.
●Since the output frequency of the DCO will drift with changes in stability and voltage, it cannot be used in situations where high clock accuracy is required.

3.4 DCO frequency range control

When changing MCLK by adjusting the multiplication factor N, the frequency of the FLL+ DCO will tend to the target frequency. Before MCLK stabilizes at the new frequency tap, each change to the next DCO tap requires a delay of 1024 clock cycles. It can be seen that for a large range of MCLK frequency changes, a large delay will be required to achieve stability. In response to this, the MSP430x4xx series uses a frequency segmentation mechanism to handle this large range of frequency changes. The 700kHz to 40MHz output of the DCO is divided into 5 segments, and the center frequency of each segment is based on a multiple of the typical frequency fnominal (2MHz). When used, it can be controlled by controlling the four bits FN_8, FN_4, FN_3, and FN_2 of the SCFI0 register. Table 1 lists the frequency range control method of the DCO. As can be seen from the table, by controlling these bits, the output frequency MCLK of the DCO can be changed without changing the current tap setting (in fact, the adjacent taps are immediately selected instead of adjusting one by one). Therefore, in this way, the time it takes for the DCO to adjust to the required frequency is much shorter than simply adjusting the multiplication factor. Therefore, the center frequency of the DCO should be adjusted according to the required frequency first, or the center frequency of the DCO should be adjusted in time when the MCLK changes greatly.

4. Use FLL＋ to optimize system performance

MSP430x4xx uses the above-mentioned FLL + clock module to optimize its global performance. At the same time, it also provides flexible clock configuration options, and the clock of each module can be selected by software. It can also dynamically adjust the system clock frequency according to the specific requirements of the system, thereby optimizing its performance. When using it, it can generally be carried out according to the following principles:

●If a stable and accurate low-frequency clock is required, the LFXT1 clock can be used;
●If a stable and accurate high-frequency clock is required, the LFXT2 clock can be used;
●If the system needs to be able to quickly switch from energy-saving mode to active mode, the DCO can be used to provide the system with clock MCLK/SMCLK after frequency locking. One of the outstanding advantages of FLL+ is that it can quickly reach a stable state.

When designing, it is necessary to choose a lower operating frequency as much as possible to reduce the power consumption of the system. In addition, the system also provides 5 programmable energy-saving modes to better reduce the power consumption of the system.

In addition, the oscillator of FLL+ has an automatic switching function. When DCO is not used for MCLK or SMCLK, this function can automatically turn off DCO. However, once the DCOCLK signal is used for MCLK/SMCLK, DCO will automatically turn on immediately. When an error or stop of external crystal oscillator or resonator occurs, the system clock will automatically switch to DCO mode, thereby further improving the reliability of the system.

References