TMS320C6678 power-on configuration and FPGA reset DSP

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TMS320C6678 power-on configuration and FPGA reset DSP [Copy link]

1. What is the DSP power-on reset configuration?

The big-endian, little-endian, boot mode, PCIe mode, and network coprocessor clock selection of the DSP need to be selected at power-on reset. How to select?
Rely on locking the logic level of the DSP Device Configuration pins at power-on.
How to set the logic level of the configuration pins?
Generally, there are two ways:
the first is to connect all the configuration pins of the DSP to the IO of the FPGA, and the FPGA is powered on to control it (the FPGA reset DSP program is attached at the end of the article)
. The second is through external pull-up/pull-down resistors.
Tip:
A reasonable onboard design should ensure that all device input pins are at a valid level and cannot be left floating. This can be achieved through pull-up/pull-down resistors, of course, internal pull-up or external pull-up.
The device generally implements pull-up/pull-down internally by evaluating the needs. However, some pins require external pull-up/pull-down.
(1) Device configuration pins: These pins need to be output (C6678 configuration pins and GPIO are common pins) and not driven (high impedance). Even if the internal pull-up/pull-down resistors may meet the required level,
external pull-up/pull-down is still required to ensure that the configuration is valid and to facilitate mode switching.
(2) Other input pins: If the internal pull-up/pull-down does not meet the required level, an external pull-up/pull-down is required.

2. TMS320C6678 device configuration pins
(1) LENDIAN: Determines the big and small endianness of the DSP.
(2) BOOTMODE[12:0]: Determines the self-boot mode of the DSP (see BootLoader for the C66x DSP User Guide for details).
(3) PCIESSMODE: Determines whether the PCIe subsystem is in EP, legacy EP, or RC.
(4) PCIESSEN: Determines whether the PICe subsystem is enabled. The default is not enabled.
(5) PACKSEL: Determines whether the input clock of the network coprocessor is the core clock or the PASSCLK clock.

3. DSP power-on timing
The DSP power-on timing is the power-on reset timing.
Device initialization is divided into two stages:
(1) All power supplies are stable. Different power supplies have power supply timings, as shown in the timing diagram below.
(2) RESET, POR, and RESERFULL are pulled high in sequence, and of course the clock input is stable.

Note:
(1) During the power stabilization period, POR must remain at a low level, so it must be pulled low before reset.
(2) DDRCLK and REFCLK should be triggered before POR is pulled high.
(3) Once DVDD18 power is obtained, RESETSTAT is pulled low.
Before DVDD18 power is supplied, all LVCMOS inputs and bidirectional pins cannot be driven low or pulled high.
(4) After DVDD18 is valid, RESETSTAT can be pulled high at any time. Under POR controlled boot, RESET must be pulled high before POR is pulled high.
(5) After the power is stable, POR must continue to maintain a low level for at least 100us. At this point, the power stabilization phase ends.
(6) After the power stabilization phase, the device initialization requires 500 REFCLK clock cycles. The maximum clock cycle is 33.33nsec, so a delay of 16us before the rising edge of POR is necessary. The clock must be active during the entire 16us period.
(7) After POR stabilizes at a high level, RESETFULL must remain at a low level for 24 REFCLK clock cycles.
(8) At the rising edge of RESETFULL, the device locks the level of the GPIO configuration pin and then performs configuration. The delay until the reset status bit RESETSTAT signal is pulled high is approximately 10,000 to 50,000 clock cycles.
(9) The GPIO configuration must be maintained for at least 12 REFCLK clock cycles (transitions) before the rising edge of RESETFULL. (10) The GPIO configuration
must be maintained for at least 12 REFCLK clock cycles (transitions) after the rising edge of RESETFULL.
In general:
After the power supply of each power supply is normal and the clock of the DSP is stable, drive RESET, POR, and RESETFULL to be pulled high in turn, and lock the GPIO level of the DSP reset configuration at the rising edge of RESETFULL, and then RESETSTAT is pulled high, and the DSP power-on reset is completed.

4. There are four reset modes for DSP
. The first three reset modes will trigger RESETSTAT, while local reset will not trigger RESETSTAT.
(1) Power-on reset
(2) Hardware reset
(3) Software reset
See the manual for details.
(4) Local reset

Local reset timing diagram
After power-on reset, local reset can be performed, that is, each core is reset separately.
Local reset can be triggered by the following methods:

LRESET pin
Watchdog timer, CORESEL[3:0] and RSTCFG register
LPSC MMRs (memory-mapped registers)

Generally, we do not use local reset. If after power-on reset, some cores are found to be in reset state while other cores can be connected and used, it is mostly caused by local reset. You should set LRESETNMIEN to 1 to avoid this problem.