tiny4412 clock test

The 4412 clock system was analyzed above. This article will simply test it, referring to Teacher Wei Dongshan's Linux Application Complete Development Manual 4412 (Part 1)

First experiment:

Samsung's BL1 will initialize ARMCLK to 400MHz. We turn off APLL and let ARMCLK work at 24MHz to see if the LED flashes slowly.

start.S

.text  

.globl _start  

_start:  

    ldr sp, =0x02027800   

// Before calling a C function, you must set up the stack, which is used to save the operating environment and allocate space for local variables  

// Refer to ROM manual P14, we point the stack to 1K above BL2 (1K is enough),  

// That is: 0x02020000 (iRAM base address) + 5K (for iROM code) + 8K (for BL1) + 16K (for BL2) + 1K (for stack))  

    bl main //Call the main function (the name main is not fixed and can be changed at will)  

halt_loop:  

    b halt_loop  

led.c

#define GPM4CON (*(volatile unsigned int *)0x110002E0)  

#define GPM4DAT (*(volatile unsigned int *)0x110002E4)  

void delay(volatile int time)  

{  

    for(; time > 0; time-- )  

        ;  

}  

int main(void)  

{  

    unsigned long tmp = 0;  

    int i = 0;  

/* 

 * GPM4_0-GPM4_3 are set to output function 

 */  

    tmp = GPM4CON;  

    tmp &= ~0xffff;  

    tmp |= 0x1111;  

    GPM4CON = tmp;   

/* 

 * Implement running lights 

 */  

    system_clock_init();  

    while(1)  

    {  

        GPM4DAT = i;  

        if (++i == 16)  

            i = 0;  

        delay(9999999);  

    }  

    return 0;  

}  

clock_init.c

//CMU_CPU  

#define CLK_SRC_CPU (*(volatile unsigned int *)0x10044200)  

#define CLK_DIV_CPU0 (*(volatile unsigned int *)0x10044500)  

#define CLK_DIV_CPU1 (*(volatile unsigned int *)0x10044504)  

//CMU_DMC  

#define CLK_SRC_DMC (*(volatile unsigned int *)0x10040200)  

#define CLK_DIV_DMC0 (*(volatile unsigned int *)0x10040500)  

#define CLK_DIV_DMC1 (*(volatile unsigned int *)0x10040504)  

// CMU_TOP  

#define CLK_SRC_TOP0 (*(volatile unsigned int *)0x1003C210)  

#define CLK_SRC_TOP1 (*(volatile unsigned int *)0x1003C214)  

#define CLK_DIV_TOP (*(volatile unsigned int *)0x1003C510)  

// CMU_LEFTBUS  

#define CLK_SRC_LEFTBUS (*(volatile unsigned int *)0x10034200)  

#define CLK_DIV_LEFTBUS (*(volatile unsigned int *)0x10034500)  

// CMU_RIGHTBUS  

#define CLK_SRC_RIGHTBUS (*(volatile unsigned int *)0x10038200)  

#define CLK_DIV_RIGHTBUS (*(volatile unsigned int *)0x10038500)  

// locktime  

#define APLL_LOCK (*(volatile unsigned int *)0x10044000)  

#define MPLL_LOCK (*(volatile unsigned int *)0x10044008)  

#define EPLL_LOCK (*(volatile unsigned int *)0x1003C010)  

#define VPLL_LOCK (*(volatile unsigned int *)0x1003C020)  

//APLL  

#define APLL_CON1 (*(volatile unsigned int *)0x10044104)  

#define APLL_CON0 (*(volatile unsigned int *)0x10044100)  

//MPLL  

#define MPLL_CON0 (*(volatile unsigned int *)0x10040108)  

#define MPLL_CON1 (*(volatile unsigned int *)0x1004010c)  

//EPLL  

#define EPLL_CON2 (*(volatile unsigned int *)0x1003C118)  

#define EPLL_CON1 (*(volatile unsigned int *)0x1003C114)  

#define EPLL_CON0 (*(volatile unsigned int *)0x1003C110)  

//VPLL  

#define VPLL_CON0 (*(volatile unsigned int *)0x1003C120)  

#define VPLL_CON1 (*(volatile unsigned int *)0x1003C124)  

#define VPLL_CON2 (*(volatile unsigned int *)0x1003C128)  

/* 

 * Function name: 

 * system_clock_init 

 * Function: Initialize the system clock of 4412 

 */  

void system_clock_init(void)  

{  

 /* IROM or BL1 sets APLL, 

  * This program does not start APLL. 

  * Instead, use the crystal oscillator clock to experience the LED flashing becoming slower 

  */  

   CLK_SRC_CPU = 0x0;  

}  

Makfile

objs := start.o led.o clock_init.o  

led.bin : $(objs)  

    arm-linux-ld -Tled.lds -N -o led.elf $^  

    arm-linux-objcopy -O binary -S led.elf $@  

    arm-linux-objdump -D -m arm led.elf > led.dis  

%.o:%.c  

    arm-linux-gcc -Wall -marm -c -O2 -o $@ $<  

%.o:%.S  

    arm-linux-gcc -Wall -marm -c -O2 -o $@ $  

clean:  

    rm -f *.dis *.bin *.elf *.o  

led.lds

SECTIONS {    

. = 0x02023400;    

.text : { *(.text) }    

.rodata ALIGN(4) : {*(.rodata*)}    

.data ALIGN(4) : { *(.data*) }    

.bss ALIGN(4) : { *(.bss) *(COMMON) }    

}    

The experimental phenomenon should be that the LED flashes very slowly compared to when system_clock_init() is not added to led.c.

Second experiment:

Increase ARMCLK to 1400MHz and observe whether the LED flashes faster. Only change clock_init.c

//CMU_CPU  

#define CLK_SRC_CPU (*(volatile unsigned int *)0x10044200)  

#define CLK_DIV_CPU0 (*(volatile unsigned int *)0x10044500)  

#define CLK_DIV_CPU1 (*(volatile unsigned int *)0x10044504)  

//CMU_DMC  

#define CLK_SRC_DMC (*(volatile unsigned int *)0x10040200)  

#define CLK_DIV_DMC0 (*(volatile unsigned int *)0x10040500)  

#define CLK_DIV_DMC1 (*(volatile unsigned int *)0x10040504)  

// CMU_TOP  

#define CLK_SRC_TOP0 (*(volatile unsigned int *)0x1003C210)  

#define CLK_SRC_TOP1 (*(volatile unsigned int *)0x1003C214)  

#define CLK_DIV_TOP (*(volatile unsigned int *)0x1003C510)  

// CMU_LEFTBUS  

#define CLK_SRC_LEFTBUS (*(volatile unsigned int *)0x10034200)  

#define CLK_DIV_LEFTBUS (*(volatile unsigned int *)0x10034500)  

// CMU_RIGHTBUS  

#define CLK_SRC_RIGHTBUS (*(volatile unsigned int *)0x10038200)  

#define CLK_DIV_RIGHTBUS (*(volatile unsigned int *)0x10038500)  

// locktime  

#define APLL_LOCK (*(volatile unsigned int *)0x10044000)  

#define MPLL_LOCK (*(volatile unsigned int *)0x10044008)  

#define EPLL_LOCK (*(volatile unsigned int *)0x1003C010)  

#define VPLL_LOCK (*(volatile unsigned int *)0x1003C020)  

//APLL  

#define APLL_CON1 (*(volatile unsigned int *)0x10044104)  

#define APLL_CON0 (*(volatile unsigned int *)0x10044100)  

//MPLL  

#define MPLL_CON0 (*(volatile unsigned int *)0x10040108)  

#define MPLL_CON1 (*(volatile unsigned int *)0x1004010c)  

//EPLL  

#define EPLL_CON2 (*(volatile unsigned int *)0x1003C118)  

#define EPLL_CON1 (*(volatile unsigned int *)0x1003C114)  

#define EPLL_CON0 (*(volatile unsigned int *)0x1003C110)  

//VPLL  

#define VPLL_CON0 (*(volatile unsigned int *)0x1003C120)  

#define VPLL_CON1 (*(volatile unsigned int *)0x1003C124)  

#define VPLL_CON2 (*(volatile unsigned int *)0x1003C128)  

/* 

 * Function name: 

 * system_clock_init 

 * Function: Initialize the system clock of 4412 

 */  

void system_clock_init(void)  

{  

    /* 1. Before setting APLL, set the clock source to crystal oscillator*/  

    CLK_SRC_CPU = 0x0;  

    /* 2. Set up APLL */  

    /* 2.1 Set lock time: PDIV=3 in APLL_CON0, so APLL_LOCK = 270x3 */  

    APLL_LOCK = 270 * 3;  

    /* 2.2 Set frequency division parameters*/  

    CLK_DIV_CPU0 = 0x00160760;  

    CLK_DIV_CPU1 = 0x00000106;  

    /* 2.3 Set control parameters and enable PLL */  

    /* default value*/  

    APLL_CON1 = 0x00803800;  

    /* 

     * Set APLL's M, P, S values, APLL output = 0xAF x 24MHz / (3 x 2 ^ 0) = 1.4GHz 

     * Enable APLL 

     */  

    APLL_CON0 = (1<<31 | 0xAF<<16 | 3<<8 | 0x0);  

    /* 3. Set up MUX and use the output of APLL*/  

    CLK_SRC_CPU = 0x01000001;  

}  

At the beginning, when testing, I tried to increase only ARMCLK to 1400MHz, and the rest of the registers used the default values, but I found that the program would run away after the LED flashed a few times. According to the figure below, most of the DIV division coefficients are 1 when the default values ​​are used, so for example, ACLK_COREM0 will also be 1400MHz, but they cannot withstand such a high operating frequency.

Samsung gives the frequency value in the high-performance state. I configured the frequency of the CPU part to below the recommended value in the table, and the program ran normally.