Samsung Electronics' 2nm process EUV exposure layers increased by more than 30%, and the future SF1.4 node is expected to exceed 30 layers

On July 23, South Korean media The Elec reported on the 17th of this month that Samsung Electronics' 2nm advanced process, which it expects to launch next year, will increase the number of EUV exposure layers by more than 30% compared to the existing 3nm process, reaching the "mid-to-late 20~30" range.

Korean media reported that the number of exposure layers at the same node is not completely fixed, depending on the nature of the product. However, in general, the average number of EUV exposure layers for Samsung Electronics' 3nm process is only 20;

In the SF1.4 process, which is expected to be mass-produced in 2027, the number of EUV exposure layers is expected to exceed 30.

▲ ASML's new generation 0.33NA EUV lithography machine NXE:3800E

With the evolution of advanced processes, the requirements for transistor size have become increasingly stringent. Using EUV lithography instead of traditional DUV in the exposure layer can achieve higher lithography accuracy, further improve transistor density, and accommodate more integrated circuits per unit area.

Against this backdrop, advanced logic foundries are actively purchasing ASML’s EUV machines.

Take TSMC as an example. According to previous reports by IT Home, it will receive a total of more than 60 EUV lithography machines this year and next year. Korean media estimates that TSMC will have more than 160 EUV lithography machines by the end of 2025.

In addition, the use of EUV lithography in the DRAM memory industry is also increasing:

In the sixth-generation 20~10nm process (i.e. 1c nm, 1γ nm), Samsung Electronics used 6~7 EUV layers, SK Hynix used 5 EUV layers, and Micron also introduced EUV lithography for the first time at this node.