DSP28335 uses FIFO serial port interrupt

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DSP28335 uses FIFO serial port interrupt [Copy link]

1. Serial communication and parallel communication DSP controllers exchange information and communicate with external devices. There are two main communication methods: 1. Serial communication 2. Parallel communication. Parallel communication generally includes multiple data lines, multiple control lines and status lines, with fast transmission speed, many transmission lines, and high hardware overhead, which is not suitable for long-distance transmission. It is generally used inside the system, such as the XINTF interface or inside the controller, such as the DMA controller. Serial communication transmits both data information and contact control information on the communication line, with low hardware overhead and low transmission cost, but slow transmission speed, and both the sender and the receiver need a communication protocol, which can be used for long-distance communication. Serial communication can be divided into two categories: 1. Synchronous communication 2. Asynchronous communication Synchronous communication: The sender and the receiver usually use the same clock source for synchronization. The method is to include a clock signal when the transmitter sends data, and the receiver uses the clock signal to receive. Typical examples include I2C and SPI. Asynchronous communication: The clocks of the sender and receiver are not the same clock, and the data is sent and received by their own clocks. However, both parties are required to use the same nominal frequency, and a certain deviation is allowed. A typical example is SCI. 2. Introduction to 28335 SCI The F28335 processor provides a total of 3 SCI interfaces. Compared with the SCI interface of TI's C240X series DSP, it has a great improvement in function. On the basis of the original functions, new functions such as automatic detection of communication rate and FIFO buffering have been added. In order to reduce the CPU overhead during serial communication, the serial port of the F28335 supports 16-level receive and send FIFOs. FIFO buffering can also be used without using FIFO buffering. The SCI receiver and transmitter have their own independent interrupt and enable bits, and can be operated independently to achieve half-duplex communication, or simultaneously to achieve full-duplex communication. To ensure data integrity, the SCI module detects discontinuity, polarity, overrun and frame errors on the received data. To reduce the burden on software, SCI uses hardware to check the polarity and data format of the communication data. Different SCI communication rates can be configured by programming the 16-bit baud rate control register. The so-called FIFO means first-in-first-out. SCI works in FIFO mode generally because the information transmitted is not in units of one frame, but in units of information consisting of a packet composed of multiple frames. For example, one of my data packets consists of 5 frames, the first one is the control byte, and the last four bytes together form a floating point number. At this time, you can set the FIFO receive interrupt to generate an interrupt when 5 bytes are received. After setting, an interrupt will be generated only after every 5 bytes are received, instead of an interrupt for every reception. This can greatly reduce the CPU overhead. The meaning of first-in-first-out is: in an interrupt, the data you read from the FIFO receive register is the first data received, and the second data received is the second data received. The depth of 16 means that the most recent 16 received data can be saved at most. If the received data exceeds 16, an overflow will occur. The overflow can be processed by software programming. The same is true for the transmit FIFO. You can put multiple data into the transmit FIFO at one time, and then the DSP will send the data in sequence. III. The characteristics of the SCI module are as follows (these functions can be set through the corresponding registers) (1) 2 external pins: SCITXD is the SCI data transmit pin; SCIRXD is the SCI data receive pin. The two pins are multi-function multiplexed pins. If not used, they can be used as general digital I/O. (2) Programmable communication rate, 64K communication rates can be set. (3) Data format: ◇ 1 start bit; ◇ 1~8 bit programmable data word length; ◇ Odd, even or invalid parity bit mode can be selected; ◇ 1 or 2 stop bits. (4) 4 error detection flags: parity error, overrun error, frame error and discontinuity detection. (5) 2 ways to wake up multi-processors: idle line wake-up (Idle-line) and address bit wake-up (AddressBit). (6) Full-duplex or half-duplex communication mode. (7) Double buffered receive and transmit functions. (8) Transmit and receive can use two modes: interrupt and status query. (9) Independent transmit and receive interrupt enable control. (10) NRZ (Non Return to Zero) communication format. (11) 13 SCI module control registers, starting at address 7050H. (12) Automatic communication rate detection (an enhanced function compared to F140x). (13) 16-level transmit/receive FIFO (an enhanced function compared to F240x). IV. Main functional units of SCI (1) 1 transmitter (TX) and related registers. ◇ SCITXBUF: transmit data buffer register, storing the data to be transmitted (loaded by the CPU); ScicRegs.SCITXBUF=a; //Write data into the data buffer register to transmit the data ◇ TXSHF register: transmit shift register, receives data from the SCITXBUF register and shifts the data to the SCITXD pin, shifting 1 bit of data at a time. （2）1 receiver (RX) and related registers. ◇ RXSHF register: receive shift register, shifts data from SCIRXD pin, 1 bit at a time; ◇ SCIRXBUF:The receive data buffer register stores the data to be read by the CPU. The data from the remote processor is loaded into the register RXSHF, and then loaded into the receive data buffer register SCIRXBUF and the receive emulation buffer register SCIRXEMU. (3) A programmable baud rate generator. (4) Control and status registers mapped by data memory.