TSMC unveils approach to migrating analog designs to 3nm

According to semiwiki, the design and migration of analog cells is completely different from digital cells because the inputs and outputs of analog cells typically have continuously variable voltage levels over time rather than just switching between 1 and 0. TSMC’s Kenny Hsieh spoke on the topic of analog design migration at a recent North American OIP event.

Simulation Cell Challenge

From TSMC N7 to N5 to N3, the number of analog design rules has increased dramatically, and more layout effects need to be considered. Analog units tend to be irregular in height, so there is no abutment like standard units. The placement of nearby transistors affects the performance of adjacent transistors, requiring more time to verify.

TSMC's approach to analog cells starting with the N5 node is to use a layout with a fixed cell height, a base that supports the cells to form an array, reuse pre-drawn layouts from Metal 0 and below, and is silicon proven. Inside the PDK of the analog unit is the active unit, plus all other parameters: CMOS, guard ring, CMOS tap, varactor, etc.

Simulation units now use fixed heights, are placed in tracks, where you can use abutments and even customize transitions, taps and guard areas. All possible combinations of simulation units are exhaustively pre-validated.

Analog unit

With this simulated cell approach, there is uniform oxide diffusion (OD) and polysilicon (PO), resulting in increased silicon yield.

Simulation cell layout

Automation simulation cell layout

By constraining the analog transistors within the analog cells to use more regular patterns, it becomes easier to use layout automation such as: automatic layout using templates, automatic routing with electrically aware width and space, and adding spare transistors to support the design process. any ECO that appears later.

General layout of simulated cells

When migrating between nodes, the schematic topology is reused, while the width and length of each device does change. The settings for APR are adjusted for each analog component in the unit. APR constraints on analog metrics such as current and parasitic matching make this process smarter. To support the ECO process, there is an automatic spare transistor insertion function. Since 2021, both Cadence and Synopsys have been working with TSMC to enable this improved approach to analog automation.

Migrating analog circuits to a new process node requires a series of device mapping, circuit optimization, layout reuse, analog APR, EM and IR repair, and post-layout simulation. During mapping, an Id saturation method is used, where devices are automatically identified based on their context.

Pseudo post-layout simulation can use estimated values ​​and some fully extracted values ​​to shorten the analysis loop. Cadence and Synopsys enhancements to IC layout tools now support schematic migration, circuit optimization and layout migration steps.

Use automated steps and a template approach to migrate the VCO layout from N4 to the N3E node, reusing the placement and orientation of differential pairs and current mirror devices. Comparing the new automated migration method with the manual method, where the manual migration took 50 days, the automation only took 20 days, resulting in a 2.5x increase in productivity. Early EM, IR and parasitic RC inspection is the basis for productivity improvements.