Understand semiconductor packaging technology in one article!

Electronic packaging is an indispensable process after the production of integrated circuit chips, and it is the bridge from device to system. The packaging production link has a great impact on the quality and competitiveness of microelectronic products. According to the current international popular view, in the overall cost of microelectronic devices, design accounts for one-third, chip production accounts for one-third, and packaging and testing also account for one-third. It can be said that one-third of the world is occupied.

The development of packaging research is so rapid on a global scale, and the challenges and opportunities it faces are unprecedented since the advent of electronic products; the number and breadth of issues involved in packaging are also rare in many other fields. It is a new high-tech discipline with a very strong comprehensiveness, from materials to processes, from inorganic to polymers, from large-scale production equipment to computational mechanics.

The original definition of packaging is to protect circuit chips from the influence of the surrounding environment (including physical and chemical influences).

Chip packaging is a process that uses (membrane technology) and (micro-machining technology) to arrange, fix and connect chips and other elements on a frame or substrate, lead out the wiring terminals and fix them by potting with a plastic insulating medium to form an overall structure.

Electronic packaging engineering: connecting and assembling elements such as substrates, chip packages and discrete devices according to the requirements of electronic complete machines to achieve certain electrical and physical properties, and transforming them into complete devices or equipment in the form of complete machines or systems.

Integrated circuit packaging can protect the chip from or reduce the impact of the external environment and provide it with a good working condition so that the integrated circuit has stable and normal functions.

Chip packaging can realize power distribution; signal distribution; heat dissipation channel; mechanical support; and environmental protection.

The first level, also known as chip-level packaging, refers to the process of gluing and fixing the circuit connections and packaging protection between the integrated circuit chip and the packaging substrate or lead frame, making it a module component that is easy to pick up, transport, and connect to the next level of assembly.

The second level is the process of combining several packages completed at the first level with other electronic components to form an electronic card.

The third level is the process of combining several circuit cards consisting of packages completed at the second level into a main circuit board to make it a component or subsystem.

The fourth level is the process of assembling several subsystems into a complete electronic product.

They are, in order, chip interconnect level (zero level packaging), first level packaging (multi-chip module), second level packaging (PWB or card) and third level packaging (motherboard).

According to the number of integrated circuit chips combined in the package, chip packaging can be divided into two categories: single chip packaging and multi-chip packaging;

According to the sealing material, it can be divided into types mainly composed of polymer materials and ceramics;

According to the interconnection method between the device and the circuit board, the package can be divided into two categories: pin insertion type and surface mount type;

According to the pin distribution pattern, there are four types of packaged components: single-sided pins, double-sided pins, four-sided pins, and bottom pins.

Common single-sided pins include single-row packages and cross-pin packages;

Double-sided pin components have dual-row packages for miniaturized packaging;

Four-sided pins have quad flat packages;

The bottom pins are available in metal can and dot array packages.

SIP: Single In-line Package SQP: Miniaturized Package MCP: Metal Composite Package

DIP: Dual In-line Package CSP: Chip Size Package QFP: Quad Flat Package

PGA: PGA package BGA: Ball Grid Array package LCCC: Leadless Ceramic Chip Carrier

The semiconductor industry has different standards for the classification of chip packaging technology levels. The most common standard in China is to classify it by the connection method between the packaged chip and the substrate. Generally speaking, the development of integrated circuit packaging technology can be divided into four stages:

Phase 1: Before the 1980s (the era of original jack components).

The main packaging technology is pin-through-hole (PTH), which is characterized by the installation of the socket on the PCB. The main forms are SIP, DIP, and PGA. Their shortcomings are that the density and frequency are difficult to improve, and it is difficult to meet the requirements of efficient and automated production.

The second stage: mid-1980s (surface mount era).

The main feature of surface mount packaging is that the leads replace pins. The leads are wing-shaped or T-shaped, with two or four sides leading out, and the pitch is 1.27 to 0.4mm, which is suitable for 3-300 leads. Surface mount technology has changed the traditional PTH plug-in form, and the integrated circuit is mounted on the PCB board through fine leads. The main forms are SOP (small outline package), PLCC (plastic lead chip carrier), PQFP (plastic quad lead flat package), J-type lead QFJ and SOJ, LCCC (leadless ceramic chip carrier), etc. Their main advantages are thin and short leads, small spacing, improved packaging density; improved electrical performance; small size, light weight; easy to automate production. Their shortcomings are that they are still difficult to meet the needs of ASIC and microprocessor development in terms of packaging density, I/O number and circuit frequency.

The third stage: The second leap occurred in the 1990s, entering the era of area array packaging.

The main packaging forms in this stage are ball grid array package (BGA), chip size package (CSP), leadless quad flat package (PQFN), and multi-chip module (MCM). BGA technology allows the pins that occupy a large volume and weight in the package to be replaced by solder balls, greatly shortening the connection distance between the chip and the system. The successful development of BGA technology has enabled the package that has always lagged behind the development of chips to finally catch up with the pace of chip development. CSP technology solves the long-standing fundamental contradiction of small chips and large packages, triggering a revolution in integrated circuit packaging technology.

The fourth stage: Entering the 21st century, we ushered in the era of stacked packaging of microelectronic packaging technology, which has brought about a revolutionary change in the concept of packaging, evolving from the original concept of packaging components to a packaging system.

At present, the mainstream of global semiconductor packaging is in the third stage of maturity. Major packaging technologies such as PQFN and BGA are being mass-produced, and some products have begun to develop towards the fourth stage.

Microelectromechanical system (MEMS) chips use stacked three-dimensional packaging.

1. The packaging process can generally be divided into two parts. The process steps before plastic packaging are called the front-end operation, and the process steps after molding are called the back-end operation.

2. Basic process flow of chip packaging technology Silicon wafer thinning Silicon wafer cutting Chip mounting, chip interconnection molding technology Deburring, cutting ribs, molding, soldering, coding and other processes

3. The back thinning technologies of silicon wafers mainly include grinding, lapping, chemical mechanical polishing, dry polishing, electrochemical etching, wet etching, plasma enhanced chemical etching, atmospheric pressure plasma etching, etc.

4. Slice first and then thin: Cut a certain depth of incision on the front side of the silicon wafer before back grinding, and then perform back grinding.

5. Thinning and dicing: Before thinning, cut the incision mechanically or chemically, then grind it to a certain thickness and use ADPE corrosion technology to remove the remaining processing volume to achieve automatic separation of the bare chip.

6. There are four ways to mount chips: eutectic bonding, soldering bonding, conductive adhesive bonding, and glass adhesive bonding.

Eutectic pasting method: using gold-silicon alloy (usually 69% Au, 31% Si), the eutectic fusion reaction at 363 degrees is used to paste and fix the IC chip.

7. In order to obtain the best eutectic mounting method, the back of the IC chip is usually plated with a layer of gold film or a pre-chip is implanted on the chip carrier of the substrate.

8. Common methods of chip interconnection include wire bonding, tape automated bonding (TAB) and flip chip bonding.

9. Wire bonding technologies include ultrasonic bonding, thermal compression bonding, and thermal ultrasonic bonding.

10. Key technologies of TAB: 1. Chip bump production technology 2. TAB carrier production technology 3. Carrier lead welding with chip bump inner lead and carrier outer lead welding technology.

11. The production process of bump chips, the technology of forming bumps: evaporation/sputtering coating method, electroplating bump production method, ball placement and template printing production, solder bump production, chemical plating coating method, ball bump production method, laser method.

12. Plastic packaging molding technology, 1 transfer molding technology, 2 injection molding technology, 3 pre-molding technology But the most important technology is transfer molding technology. The material used in transfer technology is generally thermosetting polymer.

13. The thinned chip has the following advantages: 1. Thin chips are more conducive to heat dissipation; 2. Reduce the chip packaging volume; 3. Improve mechanical properties, the thinner the silicon wafer, the better its flexibility, and the smaller the stress caused by external impact; 4. The thinner the chip, the shorter the connection between components, the lower the component on-resistance, and the shorter the signal delay time, thereby achieving higher performance; 5. Reduce the amount of dicing processing. Cutting after thinning can reduce the amount of dicing processing and reduce the incidence of chip breakage.

14. Wave soldering: The process of wave soldering includes applying flux, preheating, and passing the PCB board over a solder wave. The flux is brought to the PCB board and component pins by the combined action of surface tension and capillary phenomenon to form soldering points.

Wave soldering is a process in which molten liquid solder is pumped to form a solder wave of a specific shape on the liquid surface of the solder tank. The PCB with components is placed on a conveyor chain and passes through the solder wave at a specific angle and a certain depth to achieve the soldering process of the solder joints.

Reflow soldering: It is a group or point-by-point soldering process that achieves mechanical and electrical connection between the solder ends or pins of surface mounted components and the pads of the printed circuit board by pre-applying an appropriate amount and form of solder on the PCB soldering parts, then placing the surface mounted components, and then re-melting the solder paste pre-distributed on the pads of the printed circuit board.

15. Wire bonding (WB): Thin metal wires or metal strips are bonded sequentially on the pads of the chip and lead frame or package substrate to form circuit interconnections. Wire bonding technologies include ultrasonic bonding, thermal compression bonding, and thermal ultrasonic bonding.

Tape automated bonding (TAB): A technical process that connects the chip pads to the I/O of the electronic package or the metal wiring pads on the substrate using metal foil wires with lead patterns.

Flip chip bonding (FCB): A method in which the chip is face down and the chip pads are directly interconnected with the substrate pads.

16. Chip interconnection: Connect the chip pad to the I/O of the electronic package or the metal wiring pad on the substrate. Only when the circuit connection between the chip and the package structure is achieved can the existing functions be exerted.

As the Internet of Things era and global terminal electronic products gradually move towards multi-functional integration and low-power design, the SiP technology that can integrate multiple bare chips in a single package has attracted increasing attention. In addition to the existing large packaging and testing companies actively expanding SiP manufacturing capacity, foundry companies and IC substrate manufacturers are also competing to invest in this technology to meet market demand.

Definition of SIP

According to the definition of the International Route to Semiconductor Society (ITRS): SiP is a single standard package that assembles multiple active electronic components with different functions and optional passive devices, as well as other devices such as MEMS or optical devices, to achieve certain functions, forming a system or subsystem.

Therefore, from an architectural point of view, SiP integrates multiple functional chips, including processors, memory and other functional chips in one package to achieve a basically complete function.

Definition of SOC

Integrate ICs with different functions into one chip. This method can not only reduce the size, but also reduce the distance between different ICs, and improve the computing speed of the chip. SoC is called system-level chip, also known as system on chip, which means it is a product, an integrated circuit with a dedicated goal, which contains a complete system and all the contents of embedded software. At the same time, it is a technology that is used to realize the entire process from determining the system function to software/hardware division and completing the design.

As packaging technology continues to evolve and terminal electronic products become thinner, lighter and smaller, the demand for SiP is gradually increasing.

SiP production lines must be composed of substrates, chips, modules, packaging, testing, system integration and other ecosystems to develop smoothly. On the contrary, if there is a lack of a complete ecosystem, it will be difficult to promote the specific implementation of SiP technology.

Since SiP technology can package multiple chips into a single package to form a system, it has the characteristics of high integration and miniaturization, and is suitable for electronic products with small size, multi-function, and low power consumption.

From the perspective of various applications, if the original independent packaging components are changed to be integrated with SiP technology, the packaging volume can be reduced to save space, and the connection lines between components can be shortened to reduce resistance and improve electrical performance. Ultimately, the advantages of replacing large circuit boards with tiny packages can be presented, while still maintaining the original functions of individual chips. Therefore, the high integration and miniaturization characteristics have made SiP a development trend in packaging technology in recent years.

In addition, because SiP completely encapsulates the relevant circuits with a package, it can increase the circuit board's resistance to chemical corrosion and stress, thereby improving the overall reliability of the product and also increasing the product life.

Compared to SoC, SiP does not require new chip design and verification, but integrates existing chips with different functions using packaging technology.

Generally speaking, the basic packaging technologies commonly used in SiP at this stage include Package on Package (PoP) technology, which is commonly used in smartphones, to stack logic ICs and memory ICs in packages. Embedded technology (Embedded), which embeds active and passive components in substrates, as well as multi-chip packages (MCP), multi-chip modules (MCM), stacking dies, PiP, TSV 2.5D IC, TSV 3D IC, etc., also belong to the category of SiP technology.

Compared with the era of personal computers, the demand for SiP is more common in mobile device products. For example, in smartphones, Internet access is already a basic feature, so Wi-Fi modules related to wireless networks will be integrated using SiP technology.

The fingerprint recognition function was developed based on security and confidentiality considerations, and its related chip packaging also requires SiP to help integrate and reduce space, making the fingerprint recognition module a market where SiP is widely used. In addition, force touch is also one of the emerging functions of smartphones, and the built-in force touch module (Force Touch) requires the assistance of SiP technology.

In addition, processor modules that integrate application processors (APs) with memory, as well as sensing-related MEMS modules, are also application areas of SiP technology.

Wearable devices/IoT drive SiP demand

The development of global terminal electronic products is constantly moving towards the trend of being thin, light, short, multifunctional, and low power, and the growth potential of SiP is increasing. After the launch of wearable products such as Apple Watch in 2015, SiP technology has been expanded to wearable products.

In addition, under the trend of the Internet of Everything, various mobile devices, wearable devices, smart transportation, smart medical care, and smart home networks will inevitably be connected and combined. It is estimated that there will be huge demand for multifunctional heterogeneous chip integration, and low power consumption will also be an important trend.

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