Beyond Moore's Law: Understanding SiP Packaging Technology in One Article

From the perspective of architecture, SiP integrates multiple functional chips, including processors, memory and other functional chips, into one package to achieve a basically complete function. It corresponds to SOC (system on chip). The difference is that system-level packaging uses different chips to be packaged side by side or stacked, while SOC is a highly integrated chip product.

1.1. More Moore vs. More than Moore: Comparison between SoC and SiP

SiP is an important implementation path to surpass Moore's Law. As we all know, Moore's Law has developed to the current stage, where is it going? There are two paths in the industry: one is to continue to develop according to Moore's Law. Products that follow this path include CPUs, memory, logic devices, etc., which account for 50% of the entire market. The other is the More than Moore route that exceeds Moore's Law. Chip development has shifted from blindly pursuing power consumption reduction and performance improvement to more pragmatically meeting market needs. Products in this area include analog/RF devices, passive devices, power management devices, etc., which account for about the remaining 50% of the market.

Two products have been developed for these two paths: SoC and SiP. SoC is the product of Moore's Law, while SiP is an important path to surpass Moore's Law. Both are products of miniaturization and micro-miniaturization systems at the chip level.

SoC and SIP are very similar. Both integrate a system including logic components, memory components, and even passive components into one unit. From the design perspective, SoC is to highly integrate the components required by the system into a chip. From the packaging standpoint, SiP is a packaging method that packages different chips side by side or stacked, and assembles multiple active electronic components with different functions and optional passive devices, as well as other devices such as MEMS or optical devices, together to achieve a single standard package with certain functions.

In terms of integration, generally speaking, SoC only integrates logic systems such as AP, while SiP integrates AP+mobile DDR. To some extent, SIP=SoC+DDR. As the integration becomes higher and higher in the future, eMMC is also likely to be integrated into SiP.

From the perspective of packaging development, SoC was once established as the key and development direction of future electronic product design due to the requirements of electronic products in terms of volume, processing speed or electrical characteristics. However, as the production cost of SoC has become increasingly high in recent years, it has frequently encountered technical obstacles, causing the development of SoC to face bottlenecks, and the development of SiP has been increasingly valued by the industry.

1.2. SiP - the inevitable path to surpass Moore's Law

Moore's Law ensures the continuous improvement of chip performance. As we all know, Moore's Law is the "Bible" of the development of the semiconductor industry. On silicon-based semiconductors, the characteristic size of transistors is halved and the performance is doubled every 18 months. While the performance is improved, the cost is reduced, which gives semiconductor manufacturers enough motivation to achieve the reduction of semiconductor feature size. Among them, processor chips and memory chips are the two types of chips that comply with Moore's Law the most. Taking Intel as an example, each generation of products perfectly follows Moore's Law. At the chip level, Moore's Law promotes the continuous advancement of performance.

PCB boards do not follow Moore's Law and are the bottleneck for improving the performance of the entire system. Corresponding to the continuous reduction in chip size, PCB boards have not changed much in recent years. For example, the standard minimum line width of PCB motherboards has been 3 mil (about 75 um) since ten years ago, and it is still 3 mil today, with almost no progress. After all, PCB does not follow Moore's Law. Due to the limitations of PCB, the performance improvement of the entire system has encountered a bottleneck. For example, since the PCB line width has not changed, the connection density between the processor and the memory has also remained unchanged. In other words, if the size of the processor and memory package does not change much, the number of connections between the processor and the memory will not change significantly. The bandwidth of the memory is equal to the bit width of the memory interface multiplied by the operating frequency of the memory interface. The output bit width of the memory is equal to the number of connections between the processor and the memory. Due to the limitation of the PCB board process, it has been 64bit and has not changed in the past ten years. Therefore, if you want to improve the memory bandwidth, you can only increase the operating frequency of the memory interface. This limits the performance improvement of the entire system.

SIP is the winning hand to solve the shackles of the system. By packaging multiple semiconductor chips and passive devices in the same chip to form a system-level chip, instead of using the PCB board as a carrier to carry the chip connections, the problem of system performance bottlenecks caused by the inherent deficiencies of the PCB itself can be solved. Taking the processor and memory chip as an example, because the density of the internal routing of the system-level package can be much higher than the PCB routing density, the system bottleneck caused by the PCB line width can be solved. For example, because the memory chip and the processor chip can be connected together by perforation, they are no longer limited by the PCB line width, so that the data bandwidth can be improved on the interface bandwidth.

We believe that SiP is not just a simple integration of chips. SiP also has the advantages of short development cycle, more functions, lower power consumption, better performance, lower cost, smaller size and lighter weight, which can be summarized as follows:

The SIP packaging process can be divided into two types: wire bonding packaging and flip chip packaging according to the connection method between the chip and the substrate.

2.1. Wire bonding packaging process

The main process of wire bonding packaging is as follows:

Wafer→Wafer thinning→Wafer cutting→Chip bonding→Wire bonding→Plasma cleaning→Liquid sealant potting→Assembly solder balls→Reflow soldering→Surface marking→Separation→Final inspection→Testing→Packaging.

• Wafer Thinning

Wafer thinning refers to grinding the wafer from the back side by mechanical or chemical mechanical (CMP) methods to thin the wafer to a suitable level for packaging. As the size of the wafer is getting larger and larger, in order to increase the mechanical strength of the wafer and prevent deformation and cracking during processing, its thickness has been increasing. However, as the system develops in the direction of being thinner and shorter, the thickness of the module after chip packaging is becoming thinner and thinner. Therefore, before packaging, the thickness of the wafer must be thinned to an acceptable level to meet the requirements of chip assembly.

• Wafer cutting

After the wafer is thinned, it can be diced. Older dicing machines are manually operated, but now most dicing machines are fully automated. Whether it is partial scribing or complete separation of silicon wafers, a saw is currently used because it produces neat edges with little debris and cracks.

• Die bonding

The cut chip should be mounted on the middle pad of the frame. The size of the pad should match the size of the chip. If the pad size is too large, the lead span will be too large, and the stress generated by the flow during the transfer molding process will cause the lead to bend and the chip to move. The mounting method can be soldered to the substrate with soft solder (referring to Pb-Sn alloy, especially alloy containing Sn), Au-Si low eutectic alloy, etc. The most commonly used method in plastic packaging is to use a polymer adhesive to stick it to the metal frame.

• Wire Bonding

The lead wires used in plastic packaging are mainly gold wires, with a diameter of 0.025mm to 0.032mm. The length of the lead wire is usually between 1.5mm and 3mm, and the height of the arc can be 0.75mm higher than the plane where the chip is located.

Bonding technologies include hot pressing welding and hot ultrasonic welding. The advantages of these technologies are that they are easy to form a spherical shape (i.e., solder ball technology) and prevent gold wire oxidation. In order to reduce costs, other metal wires, such as aluminum, copper, silver, palladium, etc., are also being studied to replace gold wire bonding. The condition for hot pressing welding is that the two metal surfaces are in close contact, and the time, temperature, and pressure are controlled to connect the two metals. Surface roughness (unevenness), the formation of an oxide layer, or chemical contamination, moisture absorption, etc. will affect the bonding effect and reduce the bonding strength. The temperature of hot pressing welding is 300℃~400℃, and the time is generally 40ms (usually, plus procedures such as finding the bonding position, the bonding speed is two lines per second). The advantage of ultrasonic welding is that it can avoid high temperatures, because it uses 20kHz~60kHz ultrasonic vibrations to provide the energy required for welding, so the welding temperature can be lowered. Using heat and ultrasonic energy for bonding at the same time is called hot ultrasonic welding. Compared with hot pressing welding, the biggest advantage of hot ultrasonic welding is that it reduces the bonding temperature from 350℃ to about 250℃ (some people also think that the condition of 100℃~150℃ can be used), which can greatly reduce the possibility of forming Au-Al intermetallic compounds on aluminum pads, extend the life of devices, and reduce the drift of circuit parameters. The improvement in wire bonding is mainly due to the need for thinner and thinner packages. The thickness of some ultra-thin packages is only about 0.4mm. Therefore, the lead loop is reduced from the general 200μm~300μm to 100μm~125μm, so that the lead tension is very large and very tight. In addition, there are usually two ring-shaped power/ground wires on the periphery of the lead pad on the substrate. When bonding, it is necessary to prevent the gold wire from short-circuiting with it. The minimum gap must be >625μm, and the bonding wire must have high linearity and good arc shape.

• Plasma cleaning

One of the important functions of cleaning is to improve the adhesion of the film. For example, when depositing Au film on Si substrate, Ar plasma treatment removes hydrocarbons and other contaminants on the surface, which significantly improves the adhesion of Au. After plasma treatment, a layer of gray material containing fluoride will be left on the surface of the substrate, which can be removed with a solution. At the same time, cleaning is also beneficial to improve surface adhesion and wettability.

• Liquid sealant potting

Place the frame strip with mounted chips and wire bonding in the mold, heat the preformed block of the plastic encapsulation compound in a preheating furnace (preheating temperature is between 90℃ and 95℃), and then put it into the transfer tank of the transfer molding machine. Under the pressure of the transfer molding piston, the plastic encapsulation compound is squeezed into the runner and injected into the mold cavity through the gate (during the whole process, the mold temperature is kept at around 170℃~175℃). The plastic encapsulation compound solidifies quickly in the mold, and after a period of pressure maintenance, the module reaches a certain hardness, and then the module is ejected with an ejector pin, and the molding process is completed. For most plastic encapsulation compounds, after a few minutes of pressure maintenance in the mold, the hardness of the module is enough to allow ejection, but the curing (polymerization) of the polymer is not completely completed. Since the degree of polymerization (curing degree) of the material strongly affects the glass transition temperature and thermal stress of the material, it is very important to cure the material completely to reach a stable state in order to improve device reliability. Post-curing is a necessary process step to increase the degree of polymerization of the plastic encapsulation material. Generally, the post-curing conditions are 170℃~175℃, 2h~4h.

• Liquid sealant potting

There are two ball planting methods currently used in the industry: "Solder Paste" + "Solder Ball" and "Flux Paste" + "Solder Ball". The "Solder Paste" + "Solder Ball" ball planting method is recognized by the industry as the best standard ball planting method. The balls planted in this method have good weldability and glossiness. There will be no solder ball bias during the tin melting process, and it is easier to control. The specific method is to first print the solder paste on the BGA pad, and then use a ball planting machine or screen printing to add a certain size of solder ball on it. At this time, the role of the solder paste is to stick to the solder ball, and when heated, the contact surface of the solder ball is larger, so that the solder ball is heated faster and more comprehensively, so that the solder ball has better weldability with the pad after melting and reduces the possibility of false solder joints.

• Surface marking

Marking is to print indelible, legible letters and logos on the top surface of the package module, including manufacturer information, country, device code, etc., mainly for identification and tracking. There are many methods of coding, the most commonly used of which is printing, which includes ink printing and laser printing.

• Separation

In order to improve production efficiency and save materials, most SIP assembly work is carried out in an array combination mode, and is divided into individual devices after the molding and testing processes are completed. The division and segmentation can be carried out by sawing or stamping. The sawing process is more flexible and does not require many special tools. The stamping process has higher production efficiency and lower cost, but it requires the use of special tools.

2.2. Flip Chip Process

Compared with the wire bonding process, the flip chip process has the following advantages:

(1) Flip-chip technology overcomes the problem of the center distance limit of wire bonding pads;

(2) It provides more convenience for electronic designers in the design of power/ground distribution of chips;

(3) By shortening the interconnection length and reducing RC delay, a more complete signal is provided for high-frequency and high-power devices;

(4) Excellent thermal performance, a heat sink can be installed on the back of the chip;

(5) High reliability. Due to the effect of the filler under the chip, the fatigue life of the package is enhanced;

(6) Easy to repair.

The following is the process flow of flip chip soldering (the process that is the same as wire bonding will not be explained separately): wafer → pad redistribution → wafer thinning, bump making → wafer cutting → flip chip bonding, underfilling → encapsulation → assembly of solder balls → reflow → surface marking → separation → final inspection → testing → packaging.

• Pad redistribution

In order to increase the lead spacing and meet the requirements of the flip-chip process, the leads of the chip need to be redistributed.

• Making bumps

After the pad redistribution is completed, it is necessary to add bumps to the pads on the chip. The solder bump production technology can be electroplating, chemical plating, evaporation, ball placement and solder paste printing. Currently, electroplating is still the most widely used, followed by solder paste printing.

• Flip chip bonding, underfill

After the solder bumps are arranged in a grid shape on the entire chip bonding surface, the chip is mounted on the package substrate in a flip-chip manner, and the electrical connection is achieved through the bumps and the pads on the substrate, replacing the WB and TAB connection method of arranging terminals around the periphery. After the flip-chip bonding is completed, epoxy resin is used to fill the gap between the chip and the substrate, which can reduce the thermal and mechanical stress applied to the bumps, and improve the reliability by 1 to 2 orders of magnitude compared to not filling.

3.1. Main application areas

SiP has a wide range of applications, mainly including: wireless communications, automotive electronics, medical electronics, computers, military electronics, etc.

The most widely used field of wireless communication. SiP was first used in the field of wireless communication and is also the most widely used field. In the field of wireless communication, the requirements for functional transmission efficiency, noise, volume, weight and cost are getting higher and higher, forcing wireless communication to develop in the direction of low cost, portability, multi-function and high performance. SiP is an ideal solution, combining the advantages of existing core resources and semiconductor production processes, reducing costs, shortening time to market, and overcoming difficulties in SOC such as process compatibility, signal mixing, noise interference, and electromagnetic interference. The RF power amplifier in the mobile phone integrates the functions of frequency power amplifier, power control and transceiver conversion switch, which are completely solved in SiP.

Automotive electronics is an important application scenario for SiP. The application of SiP in automotive electronics is gradually increasing. Taking the engine control unit (ECU) as an example, the ECU is composed of a microprocessor (CPU), memory (ROM, RAM), input/output interface (I/O), analog-to-digital converter (A/D), and large-scale integrated circuits such as shaping and driving. The processes of various types of chips are different. At present, SiP is more commonly used to integrate chips together into a complete control system. In addition, the use of SiP in various units such as automotive anti-lock braking system (ABS), fuel injection control system, airbag electronic system, steering wheel control system, and tire low pressure warning system is also increasing. In addition, SIP technology has also been successfully applied in the rapidly growing in-vehicle office system and entertainment system.

Medical electronics require a combination of reliability and small size, as well as functionality and longevity. Typical applications in this field are implantable electronic medical devices, such as capsule endoscopes. Endoscopes are composed of optical lenses, image processing chips, RF signal transmitters, antennas, batteries, etc. Among them, the image processing chip is a digital chip, the RF signal transmitter is an analog chip, and the antenna is a passive device. Packaging these devices together in a SiP can perfectly meet the requirements of performance and miniaturization.

The application of SiP in the computer field mainly comes from the integration of processors and memory. Taking GPU as an example, it usually includes graphics computing chips and SDRAM. However, the packaging methods of the two are different. Graphics computing uses standard plastic ball array multi-chip component packaging, which is not suitable for SDRAM. Therefore, it is necessary to package the two types of chips separately and then package them together in the form of SiP.

SiP also has many applications in other consumer electronics. These include ISP (image processing chip), Bluetooth chip, etc. ISP is the core device of electronic products such as digital cameras, scanners, cameras, toys, etc. It converts optical signals into digital signals through photoelectric conversion, and then realizes image processing, display and storage. Image sensors include a series of different types of components, such as CCD, COMS image sensors, contact image sensors, charge loading devices, optical diode arrays, amorphous silicon sensors, etc. SiP technology is undoubtedly an ideal packaging technology solution.

Bluetooth system generally consists of wireless part, link control part, link management support part and main terminal interface. SiP technology can make Bluetooth smaller and smaller to meet the market demand, thus greatly promoting the application of Bluetooth technology. SiP integrates all the components (radio, baseband processor, ROM, filter and other discrete components) required for Bluetooth wireless technology functions in an ultra-small package.

Military electronic products have the characteristics of high performance, miniaturization, multiple varieties and small batches. SiP technology conforms to the application needs of military electronics, so it has a broad application market and development prospects in this technical field. SiP products involve military equipment such as satellites, launch vehicles, aircraft, missiles, radars, and supercomputers. The most typical application products are transceiver components of various frequency bands.

3.2.SiP——Tailor-made for Smartphones

The thinning and lightening of mobile phones has led to an increase in the demand for SiP. Mobile phones are the largest market for SiP packaging. As smartphones become thinner and lighter, the demand for SiP has naturally increased. From 2011 to 2015, the thickness of mobile phones of various brands has been continuously reduced. Thinning and lightening naturally places higher and higher requirements on the thickness of assembled parts. Taking the iPhone 6s as an example, the use of PCB has been greatly reduced, and many chip components will be made into SiP modules. As for the iPhone 8, it may be the first Apple mobile phone to use SiP throughout the machine. This means that the iPhone 8 can be made thinner and lighter on the one hand, and on the other hand, there will be more space to accommodate other functional modules, such as more powerful cameras, speakers, and batteries.

Looking at SiP applications from Apple products: Apple is a company that is firmly optimistic about SiP applications, and Apple has already used SiP packaging on the Apple Watch.

In addition to watches, the number of SiPs used in Apple mobile phones is also gradually increasing, including touch chips, fingerprint recognition chips, RFPA, etc.

Touch chip. In iPhone 6, there are two touch chips, provided by Broadcom and TI respectively, while in 6S, these two chips are sealed in the same package, realizing SiP packaging. In the future, TDDI will be packaged together. The new generation of 3D Touch technology is demonstrated in iPhone 6s. Touch sensing detection can penetrate the insulating material shell, and judge the touch action of human fingers by detecting the voltage change caused by human fingers, so as to realize different functions. The touch chip is to collect the voltage value of the contact point, convert these electrode voltage signals into coordinate signals after processing, and control the mobile phone to respond to the corresponding functions according to the coordinate signals, so as to realize its control function. The emergence of 3D Touch has put forward higher requirements on the processing power and performance of the touch module. Its complex structure requires the touch chip to be assembled by SiP, and the tactile feedback function enhances its operation friendliness.

Fingerprint recognition also uses SiP packaging, packaging the sensor and control chip together. Starting from iPhone 5, similar technology has been adopted.

RFPA module. The RFPA in mobile phones is most commonly in the form of SiP. The iPhone 6S is no exception. In the iPhone 6S, there are multiple RFPA chips, all of which are SiP.

According to Apple's habit, all mature technologies will be passed on to the next generation. We believe that the upcoming Apple iPhone 7 will adopt more SiP technology, and the future iPhone 7s and iPhone 8 will be more comprehensive and make greater use of SiP technology to achieve internal space compression.

4.1. Market size and penetration rate increased rapidly

2013-2016 SiP market CAGR = 15%. In 2014, the global SiP output value was approximately US$4.843 billion, an increase of about 12.4% over 2013; in 2015, with the continued growth of smartphones and the advent of wearable products such as Apple Watch, the global SiP output value is estimated to reach US$5.533 billion, an increase of 14.3% over 2014.

In 2016, although smartphones may gradually enter the mature stage and are unlikely to see significant growth, SiP will still show a growth trend as its applications become more popular. Therefore, it is estimated that the global SiP output value in 2016 will still grow by 17.4% compared to 2015, reaching US$6.494 billion.

Market penetration will increase rapidly. We expect that the penetration rate of SiP in smartphones will increase rapidly from 10% in 2016 to 40% in 2018. With the trend of thinness and lightness confirmed, SiP that can perfectly meet the requirements of thinness and lightness should be used more widely. Not only Apple, we expect domestic smartphone manufacturers to follow suit quickly. In addition, the increase in penetration rate will not only increase the number of smartphones using SiP, but also increase the number of SiPs used in smartphones. The combination of these two effects will drive the rapid expansion of the incremental market of SiP.

We estimate the market size of SiP in the smartphone market in the next three years. Assuming that the unit price of SiP decreases by 10% each year and the shipment of smartphones increases by 3% each year, we can see that the new market size of SiP in smartphones has a CAGR of 192%, which is very impressive.

4.2. From manufacturing to packaging and testing - the gradually integrated SiP industry chain

From the perspective of the transformation of the industrial chain and the changes in the industrial structure, the future electronic industry chain will no longer be just a traditional vertical chain: terminal equipment manufacturers - IC design companies - packaging and testing manufacturers, foundry factories, IP design companies, product design will also mobilize packaging manufacturers, substrate manufacturers, material factories, IC design companies, system manufacturers, foundry factories, device manufacturers (such as TDK, Murata), storage manufacturers (such as Samsung) and other cross-collaboration to jointly achieve industrial upgrading. In the future, the system will drive the further development of the packaging industry, and conversely, high-end packaging will also promote the prosperity of system terminals. In the future, there will be more and more direct connections between system manufacturers and packaging factories, and IC design companies may develop in two directions: IP design or direct sale of wafers.

In recent years, some wafer foundries have also begun to expand their business to the downstream packaging and testing end under the service demand of customers for one-time purchase (Turnkey Service), and have developed advanced packaging technologies such as SiP to create a one-stop service model to meet the needs of upstream IC design factories or system factories. However, the development of advanced packaging technologies such as SiP by wafer foundries will form a subtle competitive relationship with existing packaging and testing manufacturers. First of all, based on the advantages of wafer process, wafer foundries have the basic conditions for developing wafer-level packaging technology, and the entry threshold is not very high. Therefore, wafer foundries can continue to move towards the back-end fields such as wafer-level packaging after completing the wafer foundry-related processes based on product application trends and upstream customer needs, in order to achieve the overall customer demand goals. This may form a certain degree of competition for existing packaging and testing manufacturers.

Since it is almost impossible for packaging and testing factories to move upstream into the foundry field, wafer foundries can move into the downstream packaging and testing field based on their process technology advantages, especially in the high-end SiP field; therefore, when wafer foundries enter the SiP packaging business, their relationship with packaging and testing factories will shift from a simple upstream and downstream cooperative relationship to a subtle competitive and cooperative relationship.

On the one hand, the packaging and testing factories can develop towards differentiation to segment the market, and on the other hand, they can choose to cooperate with wafer foundries in technology, or use technology licensing and other methods to cooperate with the huge production capacity of the packaging and testing factories to accept orders for mass production and jointly expand the market. In addition, some of the process steps of the high-end heterogeneous packaging developed by wafer foundries still need the assistance of professional packaging and testing factories with existing technologies, so the two sides still have a basis for cooperation.

4.3. SiP industry targets

ASE + USI:

Among the major global packaging and testing companies, ASE acquired the electronics foundry service (EMS) company, USI, as early as 2010, and developed SiP technology by combining its own packaging technology with the module design and system integration capabilities of USI. This has enabled ASE to maintain its leading position in the field of SiP technology and to continue to receive orders from Apple, a major mobile phone manufacturer, for modules such as Wi-Fi, processors, fingerprint recognition, pressure touch, and MEMS, which has brought subsequent growth momentum to ASE.

In addition, ASE has also formed a strategic alliance with DRAM manufacturer Inotera to jointly develop TSV 2.5D IC technology in the SiP category; Inotera will provide ASE with silicon wafer production and manufacturing of silicon interposers, which will be combined with ASE's process capabilities in high-end packaging and testing to expand ASE's existing packaging product line.

In addition, ASE has also cooperated with Japanese substrate manufacturer TDK to establish a subsidiary, ASE, to produce embedded integrated circuit substrates, which can integrate more chips such as sensors and RF components on a smaller substrate, reducing SiP power consumption and making it smaller in size to meet the needs of wearable devices and the Internet of Things.

ASE's main growth driver this year will come from SiP. In 1H2016, SiP revenue was close to $2 billion. It is expected that SiP will be the driving force for the company's continued growth in the next 5-10 years. After winning a large SiP order for wearable watches from Company A, ASE's subsidiary USI Electronics also won a second smart watch SiP order from a major American manufacturer, which is scheduled to be shipped next year.

Ankor:

The world's second largest packaging and testing company, Amkor, uses its South Korean plant as its main base for developing SiP.

In addition to increasing investment in South Korea in 2016 to build advanced factories and global R&D centers, Amkor's SiP technology is currently mainly used in products such as image sensors and motion sensors. Amkor's Q2 2016 financial report shows that the demand for WLCSP and SiP from mid-to-high-end smartphones in China is the main driving force for the company's growth.

SPIL:

Siliconware Precision Industries, the world's third largest and Taiwan's second largest packaging and testing company, is developing IC integrated SiP, mainly based on fan-out packaging-on-package (FO PoP) technology. It is mainly used in smartphones. It is currently cooperating with some major mobile phone chip manufacturers on both sides of the Taiwan Strait and is expected to start mass production in 2016.

Since SPIL is relatively lacking in module design and system integration, it has recently been actively seeking a strategic alliance with EMS giant Foxconn to combine the company's module design and system integration capabilities to make the development of SiP technology more complete.

Changdian + STATS ChipPAC:

Changdian is one of the few semiconductor packaging and testing companies in China that can reach international technical standards. In 2015, it joined hands with SMIC and the National Big Fund to acquire Singapore's STATS ChipPAC for US$780 million, and its global ranking rose from sixth to fourth. The company has certain technical advantages in SIP packaging and has successfully developed a series of products such as RF-SIM, Micro SD, USB, FC-BGA, and LGA module.

STATS ChipPAC, which was originally ranked as the world's fourth largest packaging and testing company, is also actively developing SiP technology in its Korean plant. However, because its overall operating conditions are not as good as those of the top three plants, it is difficult to invest large amounts of capital to expand the scale of SiP. However, with the funds brought in by Jiangsu Changdian's acquisition of STATS ChipPAC, it will be able to combine the original STATS ChipPAC technology to continue to expand SiP. Changdian Technology will invest US$475 million to expand the SiP project. Currently, STATS ChipPAC's Korean plant has officially entered mass production, with a capacity utilization rate of more than 95%, mainly supplying customer A. We expect that in the future, as the amount of SiP in customer A's BOM increases, it will bring great flexibility to the company.

SiP represents the direction of industry development. Chip development has shifted from blindly pursuing power consumption reduction and performance improvement (Moore's Law) to more pragmatically meeting market needs (surpassing Moore's Law), and SiP is an important path to achieve this. From the perspective of terminal electronic products, SiP does not focus on the performance/power consumption of the chip itself, but on making the entire terminal electronic product thin, short, multifunctional, and low-power. With the rise of lightweight products such as mobile devices and wearable devices, the demand for SiP is becoming increasingly apparent.

The penetration rate of SiP in smartphones is increasing rapidly. The CAGR of the SiP market from 2013 to 2015 reached 16%, higher than the 7% CAGR of the smartphone market. As smartphones become thinner and lighter, the penetration rate of SiP will increase rapidly, and is expected to increase from the current 10% to 40% in 2018. We emphasize that we should pay attention to any new changes in smartphones. Before the penetration rate reaches 40%, it is a period of rapid growth worthy of attention.

From the perspective of industry configuration, SiP has not yet been fully priced in, and there is room for growth. In their Q2 financial reports, Amkor and ASE both gave that one of the reasons for the month-on-month growth came from the increase in SiP packaging. At the same time, Apple has decided to use multiple SiPs in new models, and domestic manufacturers have not yet begun to keep up. We estimate that the potential incremental space for SiP in 2018 is US$9.6 billion. From the perspective of industry configuration, the current growth of SiP has not been fully recognized by the market, and there is enough room for growth. We believe that among domestic listed companies, Changdian Technology (the acquired STATS ChipPAC provides SiP products to customer A) and Universal Scientific Industrial (Apple watch SiP supplier) will benefit deeply from the development of the SiP industry, and we recommend paying attention to them.

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