A detailed explanation of advanced extensible interfaces

This article introduces the Advanced Extensible Interface (AXI), which is an extension of AMBA.

The AXI protocol was originally designed for high-frequency systems to meet the interface requirements of a wide variety of components while allowing flexibility in how these components are interconnected. Suitable for high-frequency, low-latency designs, AXI maintains backward compatibility with previous AMBA versions of AHB and APB.

Understanding AXI will give you a deep understanding of how SoCs work while making you a well-rounded designer.

AXI Architecture

Recall that AHB (Advanced High-Performance Bus) is a single-channel bus that multiple masters and slaves use to exchange information. A priority arbiter determines which master is currently using the bus, while a central decoder performs slave selection. Operations are performed in bursts and may take multiple bus cycles to complete. Each burst transfer consists of an address and control phase, followed by a data phase.

AXI is similar in concept but uses multiple dedicated channels for reading and writing. AXI is burst-based like its predecessor and uses similar address and control phases before data exchange. AXI also includes many new features including out-of-order transactions, unaligned data transfers, cache support signals, and low-power interfaces.

AXI Channels

There are five independent channels between AXI masters and slaves. They are:

Read address channel

Read data channel

Write address channel

Write data channel

Write response channel

The address channel is used to send address and control information when performing basic handshake between the master and slave. The data channel is where the information to be exchanged is placed.

The master reads data from the slave and writes data to the slave. The read response information is placed on the read data channel, while the write response information has a dedicated channel. In this way, the master can verify that the write transaction has been completed.

Figure 1 shows an AXI master and slave devices connected via five AXI channels.

Figure 1. AXI Channel

Each data exchange is called a transaction. A transaction consists of address and control information, the data being sent, and any response information. The actual data is sent in bursts consisting of multiple transfers. Figure 1 shows a read and write burst consisting of four beats or data transfers.

We will discuss outbreaks in more detail later in this article.

AXI Signals

Each AXI channel has a number of signals associated with it, much like the AHB, ASB and APB signals in previous AMBA versions. There are two global signals called ACLK and ARESETn. These are the global clock and reset signals for the system respectively. The "n" suffix on ARESETn indicates that the signal is active low.

Figure 2 shows the signals corresponding to the read channels as well as the global signals.

Figure 2. Read address, read data, and global signals

Each channel has an ID tag for out-of-order transactions. Any transactions with the same ID must remain in order, but transactions with different IDs can complete in any order. This allows faster transactions to complete before slower transactions, even if the slower transaction was issued first. For example, if a master is writing data to multiple slaves, the transaction ID will allow the faster slave to complete faster.

The bus width is implementation specific, but these signals are shown for a 32-bit bus width. The RLAST signal is used by the slave to signal to the master that the last data item is being transferred.

Other notable signals include the burst size, length, and type. The VALID and READY signals are used for handshaking between the master and the slave. These will be discussed later in this article.

Cache, lock, and protection signals are used for caching, exclusive access (atomic operation), and illegal access protection, respectively.

Figure 3. Write address, data, and response signals

Figure 3 shows the write address, data, and response signals. These signals mirror the read signals above, but are used by the master to send data to the slave. WLAST signals the slave that the last data item is being sent. A dedicated write response signal allows the master to know that the write transaction completed successfully.

For a more detailed description of these signals, refer to AMBA Version 3.0, specifically the AMBA AXI Protocol v1.0 Specification.

AXI Transactions

As mentioned earlier, AXI data transfers are called transactions. Transactions can be in the form of reads or writes and include address/control information, data, and responses. Data is sent in bursts that include multiple data items called beats. To synchronize the sending and receiving of data, the AXI master and slave perform a handshake at the beginning of a transaction using the READY and VALID signals.

Channel Handshake

Each AXI channel contains a VALID and a READY signal. These are used to synchronize and control the transfer rate. The important thing to remember here is that the source or sender uses the VALID signal to indicate that data or control information is available. The destination or receiver issues the READY signal when it is actually able to use the information. Therefore, a transfer can only occur when both the VALID and READY signals are asserted.

Figure 4 shows the AXI handshake in action. Note that information transfer (indicated by arrows) occurs only when both VALID and READY are high, whichever is asserted first. Also note that AXI uses the rising edge of the clock for all transfers.

Figure 4. AXI handshake mechanism (adapted from AXI specification v1.0)

An important note in the AXI specification is that the VALID signal of one component must never depend on the READY signal of another component. READY can wait for the VALID signal, but it does not have to. Following these rules eliminates the possibility of deadlock. If VALID depends on READY and READY depends on VALID, it is easy to see that neither signal will be asserted because each is waiting for the other.

AXI Burst

Data exchanges in AXI are in the form of bursts. Each burst consists of multiple beats or data transfers. Control information sent at the beginning of a transaction indicates the length, size, and type of the burst being transferred.

AXLEN[3:0], where X stands for R or W, indicates the number of beats in a burst. Due to the 4-bit width, this means that there can be up to 16 transfers in a burst. AXLEN = b0000 means one beat per burst. The values ​​of b0001, b0010, and b0011 represent 2 beats, 3 beats, and 4 beats, respectively. This pattern continues until 16. The component must complete all beats specified by AXLEN, regardless of whether data is used.

AXSIZE[2:0] specifies how many bytes are in each beat of the burst. Each bit in AXSIZE represents another power of 2, "000" represents 1 byte per beat, and "111" represents a maximum of 128 bytes per beat. The size of these beats cannot exceed the bus width.

AXBURST[1:0] determines the type of burst to be performed.

There are three types of bursts in AXI. They are:

Fixed Burst

Increasing burst

Package outbreak

In fixed burst, the address does not change in each beat. A typical application is FIFO queue/buffer.

Incrementing burst represents a more typical type of transfer where the transfer address is incremented after each beat. You can think of it as an offset from a base address.

The final burst type is the wrap around burst. A wrap around burst is similar to an incrementing burst, except that there is a wrap around boundary where once the address has incremented to that point it wraps around to a lower address.

Figure 5 shows a simplified view of the three different types of AXI bursts.

Figure 5. AXI burst types

AXI Interconnect

The AXI interconnect allows multiple masters and/or multiple slaves to be connected to each other. The AXI specification defines the interface between masters and slaves, masters and the interconnect, and slaves and the interconnect.

In practice, the interconnect consists of slave interfaces connected to AXI masters and master interfaces connected to AXI slaves. What happens in the interconnect—that is, how different masters communicate with different slaves—depends on the implementation. The interconnect can allow a shared address bus, a shared data bus, both, or neither.

In the next article, we will learn about AXI interconnects, how they work, and how to use them in your designs.

in conclusion

This article is a basic introduction to the Advanced Extensible Interface (AXI) protocol. We looked at the old version of AXI specified in AMBA 3rd edition. As I mentioned above, you can refer to AMBA AXI Protocol v1.0 (about a hundred pages) for a more in-depth look at the first version of AXI. AXI saw some major changes in AMBA Revision 4, with new versions of AXI such as AXI4, AXI4-Lite, and AXI4-Stream.

Future AMBA articles will discuss AXI4 and the ACE protocol (AXI Coherency Extensions) for system-level cache coherency between components. AXI has become a widely used protocol in modern SoC designs. When learning AXI, simpler bus protocols like Avalon and Wishbone will become much easier.