Hybrid bonding takes center stage

Latest update time：2024-06-05

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Last week at the IEEE Electron Components and Technology Conference (ECTC), researchers advanced the latest advances in a technology critical to cutting-edge processors and memory. The technique, called hybrid bonding, stacks two or more chips on top of each other in the same package, allowing chipmakers to increase the number of transistors in processors and memory despite an overall slowdown in the traditional transistor scaling that once defined Moore's Law.

Research teams from major chipmakers and universities, including Applied Materials, Imec, Intel and Sony, have demonstrated hard-won improvements that could enable record-breaking density of connections between 3D stacked chips, about 7 million per square millimeter of silicon.

All of these connections are necessary because of the new nature of semiconductor advances, Intel’s Yi Shi told engineers at ECTC. As Ann Kelleher, general manager of technology development at Intel, explained to IEEE Spectrum in 2022, Moore’s Law is now governed by a concept called system technology co-optimization (STCO). In STCO, a chip’s functions, such as cache, input/output, and logic, are separated out and manufactured using the best manufacturing technology for each function.

Hybrid bonding and other advanced packaging techniques can then put them back together so they work like a single piece of silicon. But that’s only possible with high-density connections that can shuttle bits between the silicon with little latency or energy consumption.

Hybrid bonding isn’t the only advanced packaging technology being used today, but it offers the highest density of vertical connections. Chris Scanlan, senior vice president of technology at Besi, said hybrid bonding dominated at ECTC, accounting for about one-fifth of the research presented, and that the company’s tools were behind several breakthroughs.

In hybrid bonding, copper pads are constructed on the top surface of each chip. The copper is surrounded by an insulating layer (usually silicon oxide), and the pads themselves are slightly recessed into the insulating layer surface. After the oxide is chemically modified, the two chips are pressed together face to face so that the recessed pads are aligned with each other. The sandwich is then slowly heated to expand the copper into the gap, connecting the two chips.

Hybrid bonding, which can be used to connect a single die to a wafer full of larger dies, or to bond two wafers full of the same-sized dies together, is more mature than the former, in part because of its use in camera chips. Imec, for example, has reported some of the densest wafer-to-wafer (WoW) bonds ever made, with a bond distance (or pitch) of just 400 nanometers. The same research center has achieved a 2-micron pitch in a chip-to-wafer (CoW) scenario. (Commercial chips today have connections at about 9 microns.)

“With equipment, wafer-to-wafer alignment is easier than chip-to-wafer alignment. Most microelectronics processes are done on [whole] wafers,” said Jean-Charles Souriau, head of integration and packaging science at French research institute CEA Leti. However, chip-to-wafer (or die-to-wafer) technology has made its mark in high-end processors such as AMD’s Epyc series, which is used to assemble the computing cores and cache memory in its advanced CPUs and AI accelerators.

To push both approaches to closer and closer pitch, researchers are focusing on making the surface slightly flatter, allowing bonded wafers to stick together better and reducing the time and complexity of the entire process. Getting all this right could ultimately mean a revolution in the way chips are designed.

In the report, we saw wafer-on-wafer (WoW) studies at the tightest pitches (500nm to 360nm), all of which put a lot of effort into one thing: flatness. To bond two wafers together with 100nm precision, the entire wafer must be almost perfectly flat. If it is bent or twisted, the entire section of material cannot be connected.

Flattening the wafers is a process called chemical mechanical planarization (CMP). It is often key to chip manufacturing, especially the part of the process that produces the interconnect layers above the transistors.

“CMP is the key parameter for hybrid bonding that we have to control,” said Souriau. The results presented this week at ECTC take CMP to a new level, not only flattening the entire wafer but also reducing the roundness of the insulating layer between the copper pads to the nanometer level to ensure better connections.

Other research focuses on ensuring that these flat parts can be bonded together strongly enough, by experimenting with different surface materials, such as replacing silicon oxide with silicon carbonitride, or using different protocols to chemically activate the surface. Initially, when the wafers or chips are pressed together, they are held together by relatively weak hydrogen bonds, and the focus is on ensuring that everything stays in place between bonding and subsequent steps. The bonded wafers and chips are then slowly heated (a process called annealing) to form stronger chemical bonds. Exactly how strong these bonds are - and how to figure it out - is the subject of a lot of research at the ECTC.

The ultimate bond strength also comes in part from the copper connection. The annealing step causes the copper to expand over the gap, forming a conductive bridge. Controlling the size of the gap is key, explains Samsung’s Seung Ho Hahn. Too big and the copper won’t connect. Too small and it pushes the wafer apart. It’s a nanoscale problem, and Hahn reports on research into a new chemical process that hopes to accomplish this by etching away the copper one atomic layer at a time.

The quality of the connection is important, too. Even after the copper expands, most schemes show that the metal’s grain boundaries don’t cross from one side to the other. This crossing lowers the connection’s resistance and should improve its reliability. Researchers at Tohoku University in Japan report a new metallurgical scheme that could eventually produce large single crystals of copper that cross the boundaries. “This is a huge change,” says Takafumi Fukushima, an associate professor at Tohoku. “We are now analyzing the reasons behind this.”

Other experiments have focused on simplifying the hybrid bonding process. Some have tried to lower the annealing temperature required to form the bond (typically around 300 °C), motivated by the risk of damaging the chip from prolonged heating. Applied Materials researchers have described advances in a method that could drastically reduce annealing time—from hours to just 5 minutes.

Chip-on-wafer (CoW) hybrid bonding is currently more useful to industry: it allows chipmakers to stack dies of different sizes together and test each one before bonding it to another, ensuring they don’t cause a fatal failure in an expensive CPU due to a single defective part.

But CoW has all the difficulties of WoW, with fewer options to mitigate them. For example, CMP is designed to flatten the wafer, not the individual die. Once the die is cut from the source wafer and tested, it is difficult to improve its bonding readiness.

Still, Intel reports a 3-micron pitch for CoW hybrid bonding, while Imec achieves 2 microns, largely by making the transferred die very flat while still attached to the wafer and keeping it exceptionally clean for subsequent processes. Both teams’ efforts use plasma etching to cut the die, rather than the conventional method of using specialized blades. Plasma doesn’t cause edge chipping, which would create debris that would interfere with connections. It also allows the Imec team to shape the die, creating chamfers to relieve mechanical stress that could break connections.

Multiple researchers told IEEE Spectrum that CoW hybrid bonding is critical to the future of high-bandwidth memory (HBM). HBM is a stack of DRAM chips on top of a control logic chip, currently 8 to 12 chips high. HBM is often placed in the same package as a high-end GPU and is critical to providing the massive amounts of data needed to run large language models such as ChatGPT. Today, HBM chips are stacked using what is called microbump technology, in which tiny solder balls between each layer are surrounded by an organic filler.

But as AI drives memory demand further, DRAM makers hope to achieve 20 or more layers in HBM chips. However, the volume taken up by microbumps means these stacks will soon be too tall to be packaged with GPUs. Hybrid bonding not only shrinks the height of HBM, it also makes it easier to remove excess heat from the package because there is less thermal resistance between its layers.

At ECTC, Samsung engineers demonstrated a hybrid bonding scheme that can make a 16-layer HBM stack. "I think it will be possible to make a stack of more than 20 layers using this technology," said Samsung senior engineer Hyeonmin Lee.

Other new CoW technologies could help bring hybrid bonding to high-bandwidth memory. Souriau said that although researchers at CEA Leti did not present research in this area at ECTC, they are working on so-called self-aligned technology. This will help secure the CoW connection using a chemical process. Some parts of each surface will become hydrophobic and some parts will become hydrophilic, allowing the surface to automatically slide into place.

At ECTC, researchers at Tohoku University and Yamaha Robotics reported work on a similar scheme, using the surface tension of water to align 5-micron pads on an experimental DRAM chip with an accuracy of better than 50 nanometers.

Researchers will almost certainly continue to push the pitch of hybrid-bond connections. Han-Jong Chia, TSMC’s system exploration program manager, told engineers at ECTC that a 200nm WoW pitch is not only possible but desirable. TSMC plans to launch a technology called backside powering within two years. (Intel plans to launch it by the end of this year.) The technology puts a chip’s thick power interconnects underneath the silicon rather than on top. With these, TSMC researchers calculate, the topmost interconnect layers can better connect to smaller hybrid-bond bond pads. Backside powering with 200nm bond pads would reduce the capacitance of 3D connections so much that the product of energy efficiency and signal delay would be nine times that of what can be achieved with 400nm bond pads.

At some point in the future, if bond pitches shrink further, it might become feasible to “fold” a circuit block so that it can be built across two wafers, Chia said. That way, some of the longer connections within a block could be shortened via vertical pathways, potentially speeding up computing and reducing power consumption.

And hybrid bonding may not be limited to silicon. “There’s a lot of progress today with silicon-to-silicon wafers, but we’re also looking at hybrid bonding between gallium nitride and silicon wafers, and glass wafers… on top of everything,” said CEA Leti’s Souriau. His organization has even described hybrid bonding research for quantum computing chips, which involves aligning and bonding superconducting niobium instead of copper.

“It’s hard to say where the limit is,” Souriau said. “Things are moving so fast.”

Reference Links

https://spectrum.ieee.org/hybrid-bonding

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