Gaoyun FPGA logic analyzer function usage

littleshrimp

Gaoyun FPGA logic analyzer function usage [Copy link]

 

Right click on the blank space of the Design tab in the previous marquee project https://bbs.eeworld.com.cn/thread-1188701-1-1.html

Create a new gao file

Select Default Settings

Determine the file name

Complete GAO file creation

Add cnt to Tirger Port0 in the following order

Check M0, right-click in the blank space in Expressions and select add

Click M0 in the calculator and confirm.

Double-click M0, select Trigger Port0 in On Trigger Port, and the data on the right is default, which means it will be triggered when cnt is 0.

Switch to the Capture Options tab and follow the steps to select the clock bus

Set the storage attempt and then add the lines to be monitored

During synthesis, because the number of bus bits to be measured * storage depth is greater than the capacity of BSRAM, it is necessary to delete unused buses or adjust the test value to a smaller value.

After layout and routing, click on the logic analyzer diagram, select download in the logic analyzer interface, and then click the download programm button to complete the download

Click the Start button to start data collection

Through the above steps, you can realize the logic analysis of internal circuits. If you set the corresponding pins as inputs and connect them to the external circuits to be analyzed, you can also use this development board as a real logic analyzer. In addition to the memory depth limitation, it is also very convenient to analyze external circuits.

soso

Very convenient, one board with multiple functions:)