Registration opens for Cadence Allegro and Sigrity seminar

" 2015 CadenceAllegro and Sigrity China Technical on Tour " . R&D experts, product design service and technical support experts from Cadence headquarters and China will share with you Cadence's latest developments in high-speed PCB design and simulation, and demonstrate Cadence's unique IC/Package/PCB collaborative design to electronic design engineers. and system-level analysis solutions.

Shanghai on October 26 ; Beijing on October 28 ; Shenzhen on October 30 ;

Xi'an on November 3 ; Chengdu on November 5

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Introduction to speech content

• Allegro Sigrity integration

  Sigrity technology is integrated on the Allegro platform to perform SI/PI analysis and wiring electrical rule checking. At the same time, some solutions for integrating Sigrity tools with the Allegro platform are introduced.

• Allegro PCB Editor - What's New inSPB16.6-2015:

  Cadence® Allegro® 16.6 release continues to provide new feature updates through quarterly incremental releases ( QIR ). The latest release of Allegro 16.6-2015 includes a series of new enhanced functions and products. By using the new functions, PCB design engineers can not only improve work efficiency, ensure design quality, but also effectively control costs.

• Sigrity 2015 what's new

  Mainly introduces the latest features of Sigrity2015 , including PowerDC multi-resistance electrothermal model extraction and power tree simulation, PowerSI VR noise crosstalk analysis, 3DFEM multi-machine parallel simulation and improved Cut-and-Stitch extraction technology, OptimizePI 's best Capacitor position estimation, SystemSI 's LPDDR4 and HDMI2.0 simulation processes, etc.

• IPC 2581-Driving modern manufacturing hand-off and collaboration for 21st century

  The IPC2581 data standard output format facilitates PCB designers to transfer unified data to PCB manufacturing and PCB assembly.

• Productivity Toolbox &DRC rules Checkwith Ravel

  ProductivityToolbox is a design toolkit based on the Cadence Allegro platform. Especially for certain special design requirements, this toolkit can help users greatly improve design efficiency. For example, shielding traces on different layers, signal trace spacing inspection on different layers, advanced mirror trace design, etc. The toolkit contains 22 efficient functions, and its application scenarios include designs in various fields of high-speed, radio frequency, and IC testing.

• Early Estimation for Power Integrity Design

  If PI engineers can start power supply evaluation in the early stages of circuit design, many PI problems can be better solved before layout and routing. This can greatly improve the efficiency of electronic design and shorten the design cycle. This early stage evaluation of power supplies includes design analysis of both DC and AC.

• Allegro Manufacture Option

  AllegroPCB Designer manufacturing options provide a set of powerful and easy-to-use PCB production-related tool solutions. This solution helps PCB engineers simplify: from PCB design -> bare board production -> component installation, the delivery documents of the entire production process. This tool module contains the following three parts of functions: DFM ( Design For Manufacturing ) inspector; document editor; panel editor.

• Automatic simulation by using tcl script

  With the development of electronic technology, SIPI simulation is increasingly used in the product design stage, which puts new demands on the efficiency of simulation. The automation of SIPI simulation is an effective solution to improve simulation efficiency. As a general EDA scripting language, TCL can facilitate automated simulation. This article mainly introduces the main functions implemented by TCL in the CadenceSigrity tool , and how to establish a simulation process through TCL scripts to improve efficiency.

• High Efficiency Cross-fabric Co-designPlanning

  OrbitIO can optimize the overall planning from chip to package and even PCB , and can observe the effect of PinAssignment at the system level . Various IC data formats such as LEF, DEF Verlog or Die Abstract can be processed by OrbitIO . OrbitIO can quickly present preliminary results or complete results of planning in IC and SiP tools at any time.

• Accelerate Routing and Tuning High-SpeedInterfaces 4X Faster

  Managing and reducing product design cycles is a major challenge in getting products to market on time and as expected. PCB engineers need a design environment that can capture their design intentions and quickly feedback conclusions, and then intelligently and automatically complete product design according to the engineers' design intentions. Allegro intelligent planning and the latest automatic interactive wiring technology can accelerate interconnection planning and wiring, and efficiently perform wiring management and engineering changes. Comprehensively improve design efficiency and shorten development cycles.

• Stacked Dies Thermal Analysis for 2.5DInterposer

  Introducing the latest stacked Die or packaging thermal analysis methods and processes based on 2.5D silicon substrates.

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