A basic question about FPGA Verilog

Fred_1977

A basic question about FPGA Verilog [Copy link]

 

27 rs232_rx0 <= rs232_rx;
28 rs232_rx1 <= rs232_rx0;
29 rs232_rx2 <= rs232_rx1;
30 rs232_rx3 <= rs232_rx2;

I don't understand what the results of these statements are going to be.

assign neg_rs232_rx = rs232_rx3 & rs232_rx2 & ~rs232_rx1 & ~rs232_rx0

littleshrimp

It seems that the data of rs232_rx is read separately and stored in rs232_rx2, rs232_rx1, and rs232_rx0 in order of priority, that is, rs232_rx2 is the earliest data, rs232_rx0 is the last data, and neg_rs232_rx is 1 when the data is 1100, otherwise it is 0.

bioger

The above four sentences should be sequential logic, with each clock cycle assigned once. The final assign should actually be the clock cycle after the falling edge of RX1 and before the falling edge of RX2, and neg_rs232_rx will have a positive pulse signal.

bigbat

The following four sentences are a shift operation;

27 rs232_rx0 <= rs232_rx;
28 rs232_rx1 <= rs232_rx0;
29 rs232_rx2 <= rs232_rx1;
30 rs232_rx3 <= rs232_rx2;

This sentence is to calculate the parity check

assign neg_rs232_rx = rs232_rx3 & rs232_rx2 & ~rs232_rx1 & ~rs232_rx0

Fred_1977

Thank you so much!

Fred_1977

After studying and pondering for a whole morning, I finally figured it out. I still need to learn the basic knowledge of numbers well and then combine it with practical application experience.

bigbat

bioger posted on 2022-6-16 08:33 The above four sentences should be sequential logic, with an assignment once per clock cycle. The final assign should actually be after the falling edge of RX1 and before the falling edge of RX2...

Brother, there can only be one state per clock cycle, which is wrong for assigning objects!

yuan2213

Learned

xwd_bp

Shift Buffer

colorjun

This is the code for UART RX to find the falling edge

孤独的单刀

Shift, tap, and then take the edge as a start signal

LilMonster00

The following are the answers I found. I think there is nothing wrong with them. Can you take a look to see if they are helpful?

These lines of Verilog code implement a logic for processing RS232 received signals. The following explains the functions of these codes:

• Lines 27 to 30 : These statements transfer a continuous signal rs232_rx from one register to another, creating a shift register chain. Specifically, rs232_rx is transferred from rs232_rx0 to rs232_rx3, forming a shift chain, and the value of rs232_rx will shift one register position to the right every clock cycle. This operation is usually used to perform timing processing on signals or create a shift register chain to implement specific functions.

• Line 31: This line of code calculates a new signal neg_rs232_rx based on the value in the shift register chain. Specifically, it performs logical operations on rs232_rx3, rs232_rx2, rs232_rx1, and rs232_rx0 to obtain a new signal value. According to the code logic, neg_rs232_rx will be a logic value 1 (high level) if and only if rs232_rx3 is 1, rs232_rx2 is 1, rs232_rx1 is 0, and rs232_rx0 is 0, otherwise it is 0. This kind of logical operation is usually used to make conditional judgments on signals or generate specific signal patterns.

In summary, the purpose of these codes is to shift the continuous RS232 receive signal and calculate a new signal neg_rs232_rx based on the shifted signal value.

LilMonster00

Fred_1977 posted on 2022-6-16 11:46 After studying and pondering carefully for a whole morning, I finally figured it out. It is still necessary to learn the basic knowledge of numbers well and then combine it with practical application experience.

Digital electronics foundation? What is digital foundation?