FPGA and DSP communication issues

XuYong虚庸

Ladies and Gentlemen, this is my first time to use FPGA, and I am designing an image data acquisition system. The data collected by FPGA is transmitted to DSP for processing. DSP uses F28335, so the XINTF interface is used to connect to FPGA (as shown in the figure). An asynchronous FIFO is designed on the FPGA side, so that DSP can read the data in FIFO in DMA mode. Now looking at the timing obtained by simulation, the full signal is always high, and the read enable signal is always high, so FIFO cannot output data. My chip select signal is only set to chip select 7, and XRD is directly connected to FPGA. I really don’t know where the problem is, please help me find the problem! Thank you in advance!

okhxyyo

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XuYong虚庸

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