FPGA button problem

sudongpo2018

FPGA button problem [Copy link]

file:///C:\Users\Suqing\AppData\Roaming\Tencent\Users\1161848701\TIM\WinTemp\RichOle\()@}D}%KV00@P4$H)JORZ41.png Is there any difference between turning on and off the comment? Why can the reset signal be written like this but the key signal cannot (key is the signal after shaping)

heningbo

Brother, your key is equivalent to a clock signal, which means that when the KEY changes, the program below will be executed once. Why is the program writing so weird?

郝旭帅

If you comment it out, the circuit will refresh the new value every time the button is pressed. If you add it, the register will not be formed. The writing method for forming a register requires that only one of the signals in the signal sensitive list is not used in the circuit.

郝旭帅

It is not recommended to write like this. It is better to connect the clock port of the register to the clock.