[Domestic FPGA Anlu high-integration low-power SF1 series FPSoC new product] Button (anti-shake) control buzzer

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[Domestic FPGA Anlu high-integration low-power SF1 series FPSoC new product] Button (anti-shake) control buzzer [Copy link]

 

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Preface

Previously, we tested the LED and buttons. This article will test the buzzer in combination with the buttons and implement button anti-shake.

process

New Construction

Reference https://en.eeworld.com/bbs/thread-1234259-1-1.html

New construction beep

Create key.v to implement key recognition and support anti-shake.

Create beep.v to implement buzzer control.

Create a top-level file top.v to instantiate the above modules to realize key control of the buzzer.

beep.v

`define PERIOD 32'd25000
`define DUTY 32'd12500

module beep(
//input
input sys_clk,
input sys_rst_n,

input key_flag,
input key_value,
output beepout
);

//reg define
reg [31:0] period_cnt;
reg [31:0] duty_cycle;
reg onoff;

//************************************************ *****
//** main code
//****************************************** ****************

assign beepout = (period_cnt >= duty_cycle && onoff) ? 1'b1 : 1'b0;

always @(posedge sys_clk or negedge sys_rst_n) begin
if(!sys_rst_n) begin
period_cnt <= 32'd0;
duty_cycle <= `DUTY;
end
else if(period_cnt == `PERIOD)
period_cnt <= 32'd0;
else
period_cnt <= period_cnt + 1'b1;
end

always @ (posedge sys_clk or negedge sys_rst_n) begin
if(!sys_rst_n) begin
onoff <= 1'b0;
end
else begin
if(key_flag && (~key_value)) begin
onoff <= ~onoff;
//if(onoff)
// beepout <= (period_cnt >= duty_cycle) ? 1'b1 : 1'b0;
//else
// beepout <= 1'b0;
end
end
end

endmodule

key.v

module key(
input sys_clk,
input sys_rst_n,

input key,
output reg key_flag,
output reg key_value
);

//reg define
reg [31:0] delay_cnt;
reg key_reg0;
reg key_reg1;

//************************************************ *****
//** main code
//****************************************** ****************
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
key_reg0 <= 1'b1;
key_reg1 <= 1'b1;
delay_cnt <= 32 'd0;
end
else begin
key_reg0 <= key;
key_reg1 <= key_reg0;
if(key_reg1 != key_reg0)
delay_cnt <= 32'd500000;
else if(key_reg1 == key_reg0) begin
if(delay_cnt > 32'd0)
delay_cnt <= delay_cnt - 1'b1;
else
delay_cnt <= delay_cnt;
end
end
end

always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
key_flag <= 1'b0;
key_value <= 1'b1;
end
else begin
if (delay_cnt == 32'd1) begin
key_flag <= 1'b1;
key_value <= key_reg1;
end
else begin
key_flag <= 1'b0;
key_value <= key_value;
end
end
end

endmodule

beep_key_top.v

module beep_key_top(
input sys_clk,
input sys_rst_n,

input key,
output beep
);

//wire define
wire key_value;
wire key_flag;

//************************************************ *****
//** main code
//****************************************** ****************

key u_key(
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),

.key (key),
.key_flag (key_flag),
.key_value (key_value)
);

beep u_beep(
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),

.key_flag (key_flag),
.key_value (key_value),
.beepout (beep)
);

endmodule

The automatically selected top-level file may not be correct for manually set

Right click on top.v and select Set As Top

constraint

From the schematic diagram, we can see

25M clock input corresponds to D7

If there is no dedicated reset button, use KEY0 H3

KEY1 and KEY2 in the schematic diagram correspond to H2 G3 corresponding to KEY0 and KEY1 in the code

Buzzer corresponding to B10

The constraints are as follows

Running Tests

Key 0 reset

Press KEY1 to make the buzzer sound, and press it again to stop the buzzer.

Summarize

The above realizes the key control of the buzzer, which is mainly based on the idea of key anti-shake.

火辣西米秀

Key anti-shake is a must for all keys. What are the characteristics of the OP's anti-shake code?

qinyunti

Hot Ximi Show posted on 2023-3-5 22:09 Key anti-shake is required for all keys. What are the characteristics of the OP's anti-shake code?

No special general practice