It is reported that Google's Tensor G5 chip is based on TSMC's 3nm process and has successfully entered the tape-out stage

On July 1, Taiwan media "China Times" recently reported that the Tensor G5 chip expected to be used in Google's flagship smartphone next year will be based on TSMC's 3nm process and has successfully entered the tape-out stage.

▲ Google Tensor SoC

Tapeout is a critical stage before the formal mass production of chips. Small-scale chip trial production is used to test whether the chip design is correct. For Google, which is developing its first mobile phone SoC entirely in-house, if it passes the tapeout, it will be a big step closer to the success of Tensor G5.

The fully self-developed Tensor G5 will mean that Google can complete all-round control of Pixel devices from chips to entire devices to operating systems and even applications, which will help achieve deeper software and hardware integration.

Ultimately, Google will be able to deploy AI applications on its own devices more quickly, create differentiated products, and stand out in the highly competitive smartphone market.

▲ Google Pixel 8a mobile phone

According to previous reports by IT Home, Google's Tensor G5 chip, code-named Laguna Beach, will use TSMC's InFo_PoP wafer-level fan-out packaging technology to achieve stacking of SoC and DRAM, supporting more than 16GB of memory.