The PCI-SIG organization officially announced that it has established a new Optical Workgroup to study the possibility of introducing an optical transmission interface for the PCIe specification, while also having the potential to develop technology-specific form factors.
“Optical links will be an important advancement for PCIe architecture as they will enable higher performance, lower power consumption, longer range and lower latency,” said Nathan Brookwood, a fellow at Insight 64. “Many data-hungry markets and applications such as cloud and quantum computing, hyperscale data centers and high-performance computing will benefit from a PCIe architecture that leverages optical links.”
“We are seeing strong industry interest in expanding the reach of the established, multi-generation, energy-efficient PCIe technology standard by enabling optical connectivity between applications,” said Al Yanes, PCI-SIG president and chairman. “PCI-SIG welcomes industry input and invites all PCI-SIG members to join the Optical Working Group, share their expertise and help shape specific working group goals and requirements.”
The PCIe standard was proposed by Intel in 2001, and version 1.0 was released in 2003 with a data transfer rate of 2.5GT/s. The PCIe 6.0 version released in early 2022 has reached 64GT/s.
Over the past 20 years, the appearance of the PCIe interface has not changed, but the internal technology has undergone tremendous changes and has always been compatible with the past and the present. However, due to the constraints of the traditional copper wire transmission mechanism, it is becoming increasingly difficult to continue to improve PCIe technology, and more and more complex auxiliary mechanisms have to be added to control signal and data integrity.
When developing newer PCIe standards, the PCI-SIG worked to minimize these issues, such as using alternative signaling methods that didn’t require higher frequencies (such as PCIe 6 with PAM-4), and using mid-range retimers as materials improved to help keep up with the higher frequencies used by the standard. But the frequency limitations of copper traces within PCBs have never been completely eliminated, which is why in recent years the PCI-SIG created an official standard for PCIe based on copper wiring.
The PCIe 5.0/6.0 cabling standard, still under work through the end of this year, provides the option of using copper cables to transmit PCIe both within a system (internal) and between systems (external). In particular, relatively thick copper cables have less signal loss than PCB traces, overcoming the immediate drawback of high-frequency communications, which is short channel reach (i.e., short signal propagation distance). While the cabling standard is intended as a replacement for PCIe CEM connectors rather than a wholesale replacement, its existence highlights the problems facing high-frequency signal transmission over copper cables, a problem that will only become more challenging once PCIe 7.0 is completed. PCIe 7.0, which is in development, continues to double to 128GT/s, with x16 bidirectional theoretical bandwidth up to 512GB/s.
Over the past 20 years, although the appearance of the PCIe interface has not changed at all, the internal technology has undergone tremendous changes and has always maintained backward and forward compatibility.
However, due to the constraints of traditional copper wire transmission mechanisms, it is becoming increasingly difficult to continue to improve PCIe technology, and more and more complex auxiliary mechanisms have to be added to control signal and data integrity.
The introduction of optical transmission technology will bring new breakthroughs to the PCIe specification. However, this transformation is still in its infancy and requires in-depth research and development. Currently, the optical working group of PCI-SIG will be committed to exploring the feasibility and potential advantages of optical transmission in PCIe, and gradually incorporating it into the PCIe technology system to provide more efficient and stable solutions for future computer communications.
The origin of PCIe
The 1980s began, when computers integrated dozens of chips on motherboards and a large number of special expansion slots for adding additional cards. For the latter, one type mainly dominated the local scene: IBM's ISA bus (Industry Standard Architecture). Although improvements to the technology were not as successful in comparison, the system as a whole became ubiquitous within the industry.
By the time the next decade rolled around, faster processors helped drive the need for better-performing expansion buses, which ultimately resulted in two new formats—Intel's PCI bus (Peripheral Component Interconnect) and VLB (VESA Local Bus) from the Video Electronics Standards Association.
Both emerged at the same time in 1992, although PCI initially appeared to be the slower of the two, as it was designed to run at a fixed 33 MHz (later specification revisions did allow for 66 MHz, but consumer PCs never really supported this). In contrast, VLB runs at the same clock as the CPU's front-side bus (FSB), allowing VLB to reach 40 or 50 MHz, depending on the CPU.
However, it is not always stable at that rate, and the latency is worse than PCI. Typical VLB expansion slots are also much larger than PCI expansion slots. Despite these advantages, it took some time for PCI to gain traction in the motherboard industry, especially in the workstation and server markets.
At the time, home PC users generally didn't have many expansion cards, nor any that placed heavy demands on the bus. However, as the 3D graphics card industry took off, that changed, and the best graphics cards came with PCI connectors. As a result, motherboards began to favor the new bus over the old one. As these graphics accelerators grew in power and games took advantage of this, the limitations of the PCI bus became apparent.
Like ISA and VLB before it, PCI is a parallel data bus - meaning that all cards in a PCI expansion slot use the same bus and must take turns transmitting and receiving data. This can be problematic for graphics cards, as they can easily take over the bus. Intel solved this problem in 1997 by developing the Accelerated Graphics Port (AGP), which provided a dedicated PCI bus for graphics cards.
As the old millennium transitioned to the new, the need for a faster bus grew. Soon after Intel introduced the PCI bus, it formed a special interest group (PCI-SIG) to support motherboard and expansion card vendors in ensuring their hardware complied with the specification. By the early 2000s, this group consisted of hundreds of members, five of which (Compaq, Dell, HP, IBM, and Microsoft) worked with Intel to replace PCI.
The PCI-SIG, codenamed 3GIO (3rd Generation I/O), announced the fruits of its labor in April 2002, introducing a new technology called PCI Express. PCIe was born from this, and its full name is Peripheral Component Interconnect Express. Since then, PCIe has been continuously improved over time to adapt to the latest bandwidth requirements of modern computers.
Currently, there are more than 800 member companies that have joined PCI-SIG. Each company follows the specifications set by PCI-SIG and develops products with different functions but interoperable and communicative. The specifications that PCI-SIG has set include PCI, PCI-X and PCI Express.
The current PCI-SIG board of directors has also been expanded to include representatives from Intel, Dell, AMD, Qualcomm, HP, Synopsys, Agilent Technologies and Nvidia.
PCI vs PCI Express
Despite the same name, PCI Express (often shortened to PCIe) and the PCI bus have very little in common. The most notable difference is that PCIe is a point-to-point system - only one device uses the bus and it is not shared with any other device. In some ways, it seems like PCIe is just an upgraded AGP, but there are also significant differences in how data is transferred.
While PCI and AGP use parallel data communications, sending and receiving multiple bits of data simultaneously, PCIe uses serial communications, sending only one bit per cycle. This approach eliminates clock skew issues that can occur and cause problems with parallel communications, ultimately allowing PCIe to run at higher clock speeds.
Idealized diagram of a PCI Express strobe
PCI has an absolute limit of 66 MHz (the extended version PCI-X can reach 533 MHz), while the slowest clock speed of PCI Express is a staggering 1250 MHz.
This speed is achieved by using low voltage differential strobes (LVDS)—a pair of signals that are 180 degrees out of phase and operate at a fraction of the voltages used by PCI and AGP.
The serial nature of PCI Express also significantly reduces the number of wires/traces required to transfer data, from 32 for PCI to only 4 for PCIe. Technically, only two are needed, one for each strobe, but since PCI Express is full-duplex, sending information in both directions simultaneously, dual sets of paired strobes are always used.
This set of four wires is better known as PCIe lanes, and the specification indicates the number of lanes used via a multiplier, for example, x1 is one lane, x4 is four lanes, and x16 is sixteen lanes.
With the way the LVDS system works, a single-lane PCIe bus can transfer data at a minimum rate of about 200 MB/s in one direction. On paper, it should be higher than this, but the information being transferred is encoded and sent in 8-bit packets, with each consecutive packet sent along one consecutive lane. As a result, the actual data rate is always lower due to the extra bits required for encoding.
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