Chiplets "Lego" opens the DIY era of UCIe Alliance to build chips

Although chiplets (small chips or core particles) are sought after by the industry and academia, they were previously only a "game for a few people". But with the birth of the UCIe industry alliance, all this will become a thing of the past. A chiplet ecosystem led by top manufacturers has begun to be built, and the new future of the chip industry development has begun to emerge.

Why the alliance?

The UCIe (Universal Chiplet Interconnect Express) Alliance includes industry giants such as Intel, TSMC, Samsung, AMD, Arm, Qualcomm, ASE, Google Cloud, Meta, and Microsoft. It aims to establish a unified die-to-die interconnection standard and create an open chiplet ecosystem.

Chiplet is seen as an important way to continue Moore's Law. By partitioning the different functional areas of a complex chip into separate chips and then combining them together using advanced packaging, it can overcome the many challenges faced by traditional SoC manufacturing (such as mask scale limits and functional limits) and significantly reduce design and production costs.

By using advanced packaging technology based on heterogeneous integration, Chiplet makes the production of complex chips no longer constrained by different processes. By expanding computing power, it improves overall performance and greatly shortens the production cycle. Major semiconductor manufacturers have begun to make plans, hoping to rely on advanced packaging technology to integrate different process processes through differentiated stacking, so that Chiplet can achieve higher efficiency.

Like all technologies, Chiplet also faces many challenges. Packaging small chips with different specifications and characteristics together, heat dissipation, stress and signal transmission are all major tests. The biggest problem is the lack of unified standards. It is difficult to match and combine chiplets developed by different manufacturers, thus limiting the development of the entire industry.

"The emergence of UCIe is equivalent to the unification of traffic rules, breaking the boundaries between different processes and fabs." He Ling (pseudonym), a senior industry insider, told Aijiwei, "Previously, each chiplet combination required a new transmission protocol. Whether the die was connected through a silicon bridge or a substrate, suppliers needed to customize it, which was too complicated for both design companies and supply chains."

He further explained, "A chiplet has several dies, which may come from different foundries with the same process, or different processes from the same foundry. To achieve connection, a specific die-to-die connection IP is required, and only when the foundries agree with each other can this bridge be built."

Unified connection standards are therefore crucial. Kurt Lender, strategic analyst of Intel's IO Technology Solutions Team, said: "The chiplet-based SoP architecture allows designers to integrate design IP and process technology from multiple suppliers, but this modularity and design freedom is only effective when designers use standardized, interoperable hardware, and the best way to achieve standardized hardware across multiple suppliers is to set a single open specification that everyone can use."

The UCIe standard developed by the UCIe Alliance means that the interface of small chips will be standardized, and users can obtain small chips for building chiplets from multiple wafer fabs, realizing true hybrid configuration. "It is equivalent to breaking down the barriers between companies and reducing the development cost of complex chips." Han Xiaomin, general manager of the consulting business department of Aiji Micro, believes that this will play a key role in improving the efficiency of the chiplet ecosystem.

Intel said the UCIe Alliance represents a diverse market ecosystem that will meet customers' needs for more customized packaging-level integration, from an interoperable, multi-vendor ecosystem that connects best-of-breed chips to chip interconnects and protocols.

Arm pointed out that UCIe is a new industry alliance that aims to establish a die-to-die interconnection standard and promote an open chiplet ecosystem, while meeting customer requirements for more customizable package-level integration, connecting best-in-class die-to-die interconnects and protocols from an interoperable and multi-vendor ecosystem.

Alliance mission: Breaking through the barriers of interconnection and packaging

There are tens of thousands of Lego blocks, and users can realize any combination by relying on a unified socket. For Chiplet, this unified socket is the interconnection interface and protocol between die-to-die.

Previous chiplet designs combined die-to-die interconnects with the company's proprietary interfaces. To expand the application scope of chiplets, open interfaces are needed for interconnection so that different small chips can communicate with each other.

Interconnection interfaces and protocols are critical for chiplets. Their design must take into account the adaptation to process technology and packaging technology, system integration and expansion requirements, and must also meet the requirements of different types of chiplet integration for performance indicators such as transmission bandwidth per unit area and power consumption per bit.

The UCIe Alliance did not take a radical approach this time, but instead chose the mature PCIe (PCI Express) and CXL (Compute Express Link) interconnect bus standards in the UCIe 1.0 specification.

PCIe provides broad interoperability and flexibility, while CXL can be used for more advanced low-latency/high-throughput connections such as memory (CXL.mem), I/O (CXL.io), and accelerators such as GPUs and ASICs (CXL.cache).

PCIe and CXL have been through multiple trials, which means that the UCIe standard is starting to run with a complete and fully verified protocol layer, which can provide reliable data transmission and link management, as well as additional customized functions such as cache consistency. More importantly, designers and chip manufacturers can use existing PCIe/CXL software, further reducing development functions.

Chen Qi, a semiconductor industry insider, commented: "After the UCIe standard is implemented, chip design will move towards a more flexible and efficient design approach to meet the diverse semi-customized needs. Therefore, chips with different processes need to be connected through a dedicated bus to achieve a balance between efficient design and cost. After the UCIe standard is determined, the integration of heterogeneous chips in the future will pave the way for bus standards."

Solving the interconnection problem is only the first step. To truly combine chiplets together, advanced packaging is ultimately required. This is why chiplets are classified as advanced packaging. However, TSMC has CoWoS/InFO, Intel has EMIB, Fovores 3D, etc., and chiplets use a variety of advanced packaging. In order to achieve greater compatibility, the UCIe1.0 standard does not cover packaging/bridging technology used to provide physical links between chiplets.

In the UCIe definition, Chiplet can be connected through fan-out packaging, silicon interposer, EMIB, or even through a common organic substrate. As long as a UCIe chiplet meets the standard (including bump pitch), it can communicate with another UCIe chiplet.

Figure 1: Packaging forms currently covered by UCIe (data source: UCIe White Paper)

It should be noted that the development of chiplet technology will eventually lead to higher density of interconnection between small chips, so it is necessary to switch from traditional bump welding to hybrid bonding. However, the UCIe 1.0 standard basically only defines 2D and 2.5D chip packaging. To cope with the continuous improvement of advanced packaging functions and density, the standard itself needs to be continuously upgraded.

Who benefits?

The initiators of the UCIe Alliance include IDM, wafer fabs, packaging houses, IP and system manufacturers. Who will be the beneficiaries?

As the initiator of the UCIe Alliance, Intel believes that integrating multiple small chips into a single package and providing product innovation in various markets is the future of the semiconductor industry and an important pillar of Intel's IDM2.0 strategy.

Figure: Intel's Pat Gelsinger proposes IDM 2.0 strategy

IDM2.0 applies the IDM model that originally served only Intel internally to customers, providing one-stop services for traditional semiconductor upstream and downstream links from chip design, customization, wafer manufacturing to packaging and testing.

The biggest difference from the IDM1.0 model is that IDM2.0 has added packaging technology. Intel has top-level 3D packaging technology, which, combined with the Chiplet ecosystem, can effectively shorten the gap in pure process technology.

Technology giants such as Amazon, Google, Apple, Microsoft, Meta and Tesla have all been Intel customers. Now, they have plans or have already adopted self-developed chips for cloud services and terminal products. One of the reasons is that Intel lacked flexible customized service capabilities in the past. If Intel's 3D packaging technology can be maximized through the Chiplet ecosystem, it is expected to meet the high-end design service needs of these customers.

In February this year, Intel officially announced a new $1 billion fund, which will prioritize investments in technical capabilities that can accelerate the time-to-market of foundry customers' products, including IP, software tools, innovative chip architectures, and advanced packaging technologies. Intel also announced a partnership with several companies in the fund alliance to create an open Chiplet Platform. This platform will leverage Intel's packaging capabilities and IP optimization for Intel Foundry Services (IFS) process technology, combined with integration and verification services to accelerate customers' time to market.

A senior industry insider pointed out that "the proposal of IDM2.0 puts Intel in a position where it can advance or retreat. After further establishing a standard language, it will have the opportunity to win more customers in the future. The retreat is that if the performance is not good, it can be outsourced, which is also in line with the 2.0 plan."