Learn PWM in a blink

The so-called PWM is to use the ratio of high-level time and waveform period to represent a number. If this number becomes a nearly continuous curve after filtering, it is DA conversion; if the voltage to control the motor is expressed by this ratio, then it is motor control. Everything that can be quantified can be expressed in PWM, which is why PWM is widely used.

Methods for generating PWM:

1. Generate a counter that rolls over after a full pulse period.

2. Generate a comparator, which outputs a high level when it reaches the proportional position, otherwise it outputs a low level. The whole process is shown in the figure below.

FPGA is essentially a digital circuit. In order to generate the results in the above figure, we need to design two circuits according to the above two-step process. The first circuit is a counter, and the second circuit is a comparator behind the counter, which monitors the counter output. Once it is higher than the count value corresponding to the duty cycle, it becomes 0, and it is 1 at other times. In this way, PWM is basically realized. This corresponds to the following two pieces of code:

//Counter circuit, cnt_cycle is the counter output count result always@(posedge clk)

begin

cnt_cycle <= (cnt_cycle == (T-1)) ? 0 : cnt_cycle + 1;

end

/ Comparator circuit, pwm_buf is the output PWM result, the red word is the counter input, and the green word is the comparator comparison line /

always@(posedge clk)

begin

pwm_buf <= (cnt_cycle < duty_cycle_buf) ? 1'b1 : 1'b0;

end

In other words, the circuit corresponding to the above two codes is as follows:

Regarding the above circuit, I would like to make a point: the implementation of the counter in FPGA is composed of an adder and a trigger. The adder outputs +1 each time, and the +1 result is given to the output terminal at the next clock. This is not the result of asynchronous 2-frequency division in the digital electronic textbook at all! In addition, I would like to emphasize again that due to the limitations of practical factors in the design of FPGA, some theoretical models in the digital electronic textbook are difficult to apply in large quantities in practice, so many structures and comprehensive results inside FPGA are different from those in the digital electronic textbook, but the basic principles of digital circuits have not changed at all!

There is one last point missing for PWM, because the input duty cycle can change continuously, that is, the comparison line in the first picture will move up and down. In order to avoid affecting the sudden value collected during the counting process, which will eventually lead to an unsmooth duty cycle, the duty cycle input will be collected only after each counting cycle is completed. This is what you see:

always@(posedge clk)

begin

if(cnt_cycle == (T-1)) duty_cycle_buf <= (duty_cycle > T-1) ? T-1 : duty_cycle;

end

Only when cnt_cycle counts a period T, the duty cycle value will be updated, that is, the comparison line will move!