xilinx vivado xdc constraint syntax

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xilinx vivado xdc constraint syntax [Copy link]

1. Purpose of Constraints

Introduce the principle of FPGA constraints, understand that the purpose of constraints is to serve the design, to ensure that the design meets the timing requirements, and to guide FPGA tools for synthesis and implementation. Constraints are the goal that tools such as Vivado strive to achieve. Therefore, the design must be reasonable first, so that it is possible to meet the constraints. Constraints in turn check whether the design can meet the timing. It mainly involves the xilinx vivado xdc constraint syntax, and gives the corresponding ISE ucf syntax. In addition, the syntax of quatus is almost compatible with xdc, and the principles are the same.

The most basic timing constraint is the clock, which has three characteristics: jitter, skew, and duty cycle distortion.

1. Jitter is divided into cycle jitter, cycle to cycle jitter and long term jitter.

2. The offset is related to the length of the clock line, the load capacitance and the number of timing units. The global clock of FPGA uses a full copper process and a tree structure, so the offset is very small and can be ignored.

3. Duty cycle distortion means the asymmetry between high and low levels, which will consume the timing margin.

2. Basic clock constraints

In the simplest case, the design has only one clock. At this time, it is necessary to constrain the period of this clock (of course, the duty cycle can also be constrained, the default is 50%). If the clock is not constrained, we will not know whether our design has timing convergence. Simply put, for example, if the system clock is 200M, then the period is 5ns, which means that the signal comes out of a register, passes through a series of combinational logic, and must be sampled by the destination register before the rising edge of the next clock arrives. Of course, the actual situation is much more complicated.

If there are many clocks in the design, which clocks must be constrained?

First is the clock that enters the FPGA from the port. Other derived clocks (such as those generated by PLL or MMCM) are the same source clocks, and the tool will automatically derive them. Then the GT's rx_clk and tx_clk must be constrained. Finally, the user's own frequency division generated ripple clock (for simple low-frequency applications) must be constrained.

create_clock -name clk_200m -period 5 [get_ports I_clk200]

3. Cross-clock domain cdc constraints

set_clock_groups –asynchronous -group [get_clocks -include_generated_clocks clk_1] \

-group [get_clocks -include_generated_clocks clk_2]

4. Input delay

Input delay and output delay are both external delays analyzed, which is exactly the opposite of the ISE ucf constraint FPGA internal delay.

5. Output delay

Assume the period is 10ns

OFFSET = OUT 4ns AFTER clock;

set_output_delay 6 -clock [get_clocks] [get_ports]

By packing the input and output registers into the IOB and constraining the slew, it is easier to meet the interface timing requirements.

Constraints in rtl

(*IOB = “true”*)

O_config_dat

Constraints in xdc

set_property IOB true [get_ports O_config_dat]

set_property SLEW FAST [get_ports O_config_dat]

littleshrimp

Picture not available

Jacktang

It will eat up the timing margin. This needs a picture to be seen clearly.