Realization of digital phase-locked adjustable frequency source based on ADF4111

Frequency synthesis technology refers to the ability to generate a large number of discrete signal frequency outputs with the same stability and accuracy from a standard reference frequency with high stability and accuracy through a series of processing, and the frequency of the output signal can be changed by digital signal control. Its main application is to provide local oscillators for up/down converted intermediate frequency or radio frequency signals. There are three basic methods of frequency synthesis: direct frequency synthesis, phase-locked frequency synthesis, and direct digital frequency synthesis. Phase-locked frequency synthesizer is the most widely used frequency synthesizer today. It has the characteristics of a large output frequency range and good spurious suppression characteristics.

In the shortwave digital receiving system, the shortwave signal received from the antenna is mixed with the local oscillator signal to obtain a 70 MHz intermediate frequency, and then the intermediate frequency signal is bandpass sampled. The stability and accuracy of the local oscillator signal have an important and direct impact on the system performance. This paper adopts frequency synthesis technology, uses ADF4111 frequency synthesizer of ADl company and FLEXlOKE series FPGA of Altera company to realize a digital phase-locked frequency source local oscillator with stable frequency, high accuracy, range of 70-90 MHz, and step interval of 1 MHz.

1 Basic principle of phase-locked loop

A phase-locked loop (PLL) is a cyclic control system based on phase negative feedback, as shown in Figure 1. A phase-locked loop consists of the following four parts:

(1) R frequency division factor, phase detector, charge pump.
(2) Loop filter, generally a low-pass filter, which filters the current output of the charge pump to drive the voltage-controlled oscillator, and its transfer factor is Z(s);
(3) The voltage-controlled oscillator has a frequency sensitivity of Kv/s;
(4) Feedback frequency division factor N.

It uses the R-division of a high-accuracy and stable crystal oscillator as the input reference frequency. The input reference frequency is used as the reference of the phase detector to compare with the output of the voltage-controlled oscillator, generating a current pulse corresponding to the phase difference of the two signals. The current pulse is integrated by the loop filter to generate a control voltage, and the high-frequency components and noise are filtered out. This voltage drives the output frequency of the voltage-controlled oscillator (VCO) to increase or decrease. When the loop is locked, the frequency difference between the input reference frequency and the N-division output of the voltage-controlled oscillator is zero, and the phase difference no longer changes with time. At this time, the control voltage is a fixed value, and the loop enters a locked state.

When the input reference clock fREFIN and the output fVCXO of the voltage-controlled oscillator have the same frequency and phase after being divided by R and N respectively, the output e(s) of the phase detector is 0, and the loop will be in a locked state. It can be deduced from the equation e(s)=FREFIN／R-FVCXO／N that when e(s)=0, fREFIN／R=FVCXO／N, that is, FVCXO=NFREIN／R.

The phase-locked frequency synthesizer integrates R, N frequency division factors, phase detector, and charge pump into one chip. It has a good suppression effect on phase noise and spurious, and is easy to debug. As a core component in communication, radar, telemetry and remote control, electronic reconnaissance and other systems, it is one of the key factors to ensure the performance of the entire electronic system. Therefore, it is currently widely used in many fields such as television, instrumentation, and communication.

2 Design of digital phase-locked frequency source

According to system requirements, the design indicators of the digital phase-locked frequency source are mainly: output frequency of 70-90 MHz; step interval of 1 MHz; output power of 9 dBm. In order to meet these three main indicators, the design of the solution and the selection of devices are considered from the following three aspects.

2.1 Output frequency

In order to obtain a high-precision frequency with an output range of 70 to 90 MHz, the design uses the high-performance phase-locked frequency synthesizer chip ADF4111 launched by ADI. The maximum frequency of its RF feedback input is 1.2 GHz, which is the maximum output frequency that the phase-locked loop can obtain, meeting the frequency output range requirements of this design. This chip can be used in wireless RF communication system base stations, wireless LANs, mobile phones, and communication detection equipment. It mainly consists of four parts:

(1) Low noise phase frequency detector (PFD).
(2) Precision charge pump (Charge Pump).
(3) Programmable preset divider. It is mainly composed of three programmable counters: A counter (6 bits), B counter (13 bits), and dual-mode preset divider (P/(P+1), P is the modulus of the preset divider). These three types of counters perform N-frequency division from the VCO output frequency to the PFD, realizing the operation of N=BP+A; the dual-mode preset divider has four working modes: 8/9, 16/17, 32/33, 64/65;
(4) Reference divider (R counter, 14 bits).

When using, registers need to be configured. In addition to configuring the chip working mode, register configuration mainly sets the input clock division factor R and VCXO input division ratio A, B, so that the two input clocks of the phase detector are equal. The relationship between the VCXO output clock and the input clock is: FVCXO=[(P×B)+A]FREFIN/R. In the formula: P is the prescaler factor; FREFIN and FVCXO are the input reference clock frequency and the output frequency of the voltage-controlled oscillator respectively.

The configuration of registers can be controlled by FPGA. FPGA is increasingly used due to its high integration, powerful functions, user programmability, and small size. In this design, the configuration of registers is also flexible and convenient. The FLEX series chip EPFlOK50EQC240-3 with the structure of Altera's 0.25μmCMOS ROM process specification is selected in the design. The FLEX series chip is a medium-density device based on the lookup table structure with high performance and low power consumption. The FPGA program development is implemented using Altera's QuartusⅡ software, and the register configuration program of ADF4111 is written in AHDL hardware description language.

The voltage-controlled oscillator that forms a phase-locked loop with the frequency synthesizer ADF4111 is POS-100 from Mini-circuit. It is a voltage-controlled oscillator with excellent performance. Its tuning voltage range is 0 to 16 V, and the corresponding output frequency range is 45 to 110 MHz. The voltage regulation sensitivity is 4.2 to 4.8 MHz/V, and the typical output power is 8.3 dBm. From its voltage-frequency relationship, it is known that when the output frequency is 90 MHz, the corresponding input voltage is between 11.5 and 12 V. When 3.3 V is added to the analog and digital power supply terminals of ADF4111 and 5 V is added to the charge pump power supply terminal, the maximum voltage of the charge pump output after the loop filter is 5 V. If the 5 V voltage is not amplified, it is obviously impossible to drive the voltage-controlled oscillator to generate a frequency of 90 MHz. Therefore, an amplifier needs to be added after the loop filter. OP191 is an amplifier with a supply voltage of 2.7 to 12 V from AD. It is mainly used in industrial control, telecommunications, remote sensing and other fields. Its supply voltage is designed to be 12 V, which can make its output voltage reach up to 12 V, which can meet the tuning voltage input requirement of the voltage-controlled oscillator output frequency of 90 MHz.

2.2 Frequency Step

The method to achieve frequency stepping is to adjust the output frequency of the voltage-controlled oscillator by changing the register configuration value of the frequency synthesizer ADF411l to achieve loop locking, and finally achieve stepping of the output frequency of the voltage-controlled oscillator.

The frequency stepping can both increase and decrease the VCO output frequency. Therefore, in the design, two buttons are used to initiate the increase and decrease instructions respectively, and the corresponding instructions for configuring the ADF411l registers are implemented through FPGA using AHDL programming.

2.3 Output power

According to the signal flow, the output of the voltage-controlled oscillator POS-100 is divided into two paths: one path is fed back to the ADF4111, and the other path is used as the local oscillator output. At this time, the output of the voltage-controlled oscillator needs to be divided into two paths through a T-type network. Here, the T-type network is a resistor splitter, as shown in Figure 2. It is widely used in situations where a source needs to drive two loads, and its purpose is to perform impedance matching of the circuit. Three 18 Ω resistors are commonly used to form a Y-type. If one of the loads is 50 Ω, it is equivalent to a T-type network with an attenuation of 6.3 dB.

The typical output power of the voltage-controlled oscillator POS-100 is 8.3 dBm. After passing through the T-type network, the signal power output as the local oscillator is 8.3-6.3=2 dBm. Obviously, the 2 dBm signal needs to be amplified, so the design uses the monolithic integrated circuit amplifier ERA-4 from Mini-circuits. It can amplify the signal frequency range of 0 to 4 GHz, and the amplification gain for 0 to 1 GHz signals is 14 dB. To ensure that the local oscillator input signal of ERA-4 is not saturated, the 2 dBm local oscillator signal is input into ERA-4 after passing through a 4 dB attenuator. At this time, the power of the local oscillator signal output from ERA-4 is 2-4+14=12 dBm. Finally, in order to obtain a local oscillator output of 9 dBm, the signal output by ERA-4 needs to be attenuated by 3 dB. The attenuator is designed with a U-type resistor matching network.

In the system, the FPGA working clock and the frequency synthesizer ADF4111 input reference clock are provided by the 40 MHz TCXO clock of WINTRON Corporation of the United States.

3 Hardware Design of Digital Phase-Locked Frequency Source

According to the digital phase-locked frequency source design scheme, the designed hardware structure is shown in Figure 3.

As the logic control center of the system, the FLEX10K50E chip integrates 50,000 gates, 2,880 logic elements, and a RAM capacity of 40,960 bits. Its main functions are:

(1) Receive the keystroke instructions for increasing or decreasing the output frequency fVCXO;
(2) Configure the frequency synthesizer ADF4111;
(3) Control the digital display tube to display the locked fVCXO value.

The design of the phase-locked loop is the key to ensure that the system can generate stable, high-precision local oscillator output. The local oscillator output from the voltage-controlled oscillator must pass through the attenuator and amplifier to ensure that the final local oscillator output power meets the index requirements. The following focuses on the circuit design of these two parts.

3.1 Phase-locked loop circuit design

The phase-locked loop circuit design mainly consists of two parts: ADF4111 design and loop filter design. These two aspects are explained below.

3.1.1 ADF4111 Design

The four 24-bit control word registers inside ADF4111 are R divider, N divider, function register and initialization register. FPGA controls the phase-locked loop by setting the control words of these four control registers.

The signals input from the outside to ADF4111 include the standard frequency source signal (40 MHz) and the control signal output by FPGA. After the standard frequency source signal is input to ADF4111, it is passed through the 14-bit R divider to obtain the phase-detection reference frequency and sent to the phase detector. The control signal consists of the clock signal CLK, the data signal DATA and the enable signal LE. Under the control of CLK, the 24-bit data signal is input from the DATA signal terminal and temporarily stored in the 24-bit input register. After receiving LE, the previously input 24-bit data reaches the corresponding latch according to the address bit. When ADF4111 receives the output frequency fed back, it first passes through the pre-division ratio factor P, passes through the A and B dividers, obtains the feedback signal after the division, and then inputs it to the phase lock. Compared with the standard frequency source signal after the division in the phase detector, the low-frequency control signal is output to control the frequency of the external VCO so that it is locked to the stability of the reference frequency.

In the design, a 40 MHz crystal oscillator is used as the standard frequency source signal. In order to obtain a step size of 1 MHz. The PFD input frequency of ADF4111 is 1 MHz. Therefore, the reference clock divider R is set to 40, and P is set to 8. From the relationship: FVCXO=[(P×B)+A]FREFIN/R, when FVCXO=70 MHz, counter A can be set to 6 and counter B to 8. Then the control words of the four control registers are set to R divider 6200AOH, N divider 200819H, function register 003092H, and initialization register 003093H. When the key sends a command to increase or decrease the local oscillator output frequency, the values ​​of counters A and B are changed, and the control register of ADF4111 is reloaded, and finally the local oscillator output frequency is changed.

3.1.2 Loop Filter Design

The design requirements of the loop filter are relatively strict. Its quality directly affects the stability of the phase-locked loop. The filter can be designed using the dedicated software ADI simPLL 3.0 provided by AD. The simulation software provides an integrated environment for the ADF series frequency synthesizer, which includes the ADI frequency synthesizer model, VCO and TCXO models. You can select the corresponding parameters to design the required loop filter. It also gives the reference phase noise, output spurious and locking process.

The wider the bandwidth of the loop filter, the shorter the lock time, but the spurious noise increases. The narrower the bandwidth of the loop filter, the lower the spurious noise, but the lock time increases. Therefore, the bandwidth selection of the loop filter needs to compromise between the two. In the design, the bandwidth is selected as 1/10 of the reference frequency of the phase detector to take both factors into account. Another factor that needs to be considered in the loop filter is the phase margin. Too small a phase margin will cause system instability, and too large a phase margin will slow down the entire system. 40°~55° is a more ideal choice. Within this range, under a certain spurious degree, the lock time can be minimized. In the design, the filter bandwidth is set to 100 kHz and the phase margin is 45°. The design and simulation results of the loop filter can be obtained using ADI SimPLL 3.0 simulation software. The resistance and capacitance values ​​are adjusted accordingly according to the final debugging. The designed circuit is shown in Figure 4.

3.2 Attenuator Design

In order to ensure that the final local oscillator output power meets the index requirements, the attenuation and amplification circuit parts are designed. In this design, the attenuator uses a π-type resistor network, which must meet both the power distribution requirements and the impedance matching requirements. When the input and output impedances of the attenuator are both 50 Ω, the 4 dB attenuator designed using CASCADE (Comptlter Aided Scientific Amplitier Design Element) software is shown in Figure 5.

4 Digital phase-locked frequency source hardware and software debugging

After completing the hardware and software design of the frequency source, system debugging is required. Debugging includes hardware debugging and software debugging.

4.1 System Hardware Debugging

After completing the system hardware circuit design and PCB production, it is necessary to use tools such as multimeters, oscilloscopes, and spectrum analyzers to debug the system to verify whether the design meets the system design requirements and whether there are any circuit errors. Hardware debugging mainly includes digital phase-locked loop debugging, pre-power-on detection, post-power-on detection, and working status debugging of each component of the module.

In the design, the data is downloaded to the FPGA using the JTAG configuration method through the USB-Blaster download cable. Downloading the configuration is the first step to verify other circuit parts in the system. The method is to design some simple logic circuits through the QutartusⅡ software, then download them to the FPGA, and use tools such as oscilloscopes to detect whether the output waveform is correct.

4.2 System software debugging

In this design, the software design part is implemented in the FPGA using the AHDL hardware programming language. It is mainly divided into two parts: one is the configuration of the ADF4111 register; the other is to realize the requirements of the key to increase and decrease the phase-locked frequency. In this design, the trigger sampling function of the digital oscilloscope is used to capture the timing logic of each pin of the FPGA configuration ADF4111 register.

The registers that ADF4111 needs to configure are three 24-bit registers. The simulation timing of programming and configuration using AHDL on Altera's QuartusⅡ platform is shown in Figure 6. Among them, R=40, A=6, B=8, and P=8.

ADF4111 has a multiplexed output pin (muxout), which can be used to check whether the register configuration is correct. In the design, this pin is set to output the PLL lock indicator and connected to a light-emitting diode. After configuration, if the indicator light is on, it means that the configuration is correct and the PLL is locked on the input clock. After configuring the ADF4111 in debugging, the PLL successfully locks on the set frequency.

After the entire design and debugging was completed, the output frequency of the digital phase-locked frequency source was tested with a spectrum analyzer. Figure 7 is the spectrum diagram at 70 MHz output. It can be seen that the frequency source output is stable. It should be noted that the local oscillator output power shown in the screenshot is -23.77 dBm. This is because the probe used to measure the local oscillator output has loss. The loss is about 33 dB after measurement. Therefore, the actual power of the local oscillator output is 9 dBm, which meets the system design requirements.

5 Conclusion

This paper uses the method of combining FPGA with frequency synthesizer ADF4111 to design a digital phase-locked frequency source. The frequency control word program required by the frequency synthesizer is written in AHDL hardware description language in FPGA to generate high-precision frequencies ranging from 70 to 90 MHz. The frequency stepping adopts the key control method, and the stepping interval is 1 MHz. The locked frequency value is displayed on the digital display tube. The PCB board is completed, and hardware and software debugging is carried out. Through the multiplexed output pin (Muxout) of ADF4111, it can be seen that the PLL successfully locks the set frequency, and the generated frequency is measured with a spectrum analyzer. The output frequency is stable, accurate, and the power meets the design index requirements. The stepping of the PLL output frequency is realized, with an interval of 1 MHz. The locked frequency value is displayed on the digital tube.

In this system, since the control word of the control word register of ADF4111 is written through FPGA, the written control word can be changed through software design to realize the output of local oscillator signals of different frequencies, so that the phase-locked loop has low phase noise and low spuriousness. It has the characteristics of fast locking, simple circuit and easy debugging. This method can change the frequency of the output signal according to the actual engineering needs. The step interval and power make this type of circuit design widely used in wireless communication equipment, providing high-quality local oscillator for the intermediate frequency and radio frequency circuits of the equipment.