Driving Timing Design of CMOS Image Sensor IBIS5-B-1300

CMOS image sensors were produced in the 1980s. Due to the low manufacturing technology of CMOS process at that time, the noise of sensors in applications was large, and the commercialization process has been slow. So far, with the continuous improvement of technology, the application scope of CMOS image sensors has been expanding, involving digital products, communications, industry, medical and other fields. Compared with CCD, CMOS image sensors have the characteristics of small size, low power consumption and low cost. Cypress's CMOS image sensor IBIS5-B-1300 is a high-performance, large dynamic range image sensor. The normal operation of the image sensor requires a correct driving timing signal. This article gives the driving timing and simulation results designed using VHDL language for the image sensor IBIS5-B-1300.

1 IBIS5-B-1300 image sensor

1.1 Chip Introduction

Cypress's IBIS5-B-1300 integrates analog image acquisition, digitization and digital signal processing functions into a single chip, and is a high-performance CMOS image sensor. This 1.3 million pixel (1 280 × 1 024) image sensor can be output in SXGA or VGA format, with a frame rate of up to 27.5 f/s (1 280 × 1 024) or 106 f/s (640 × 480).

Its main features are as follows:

(1) 6.7μm high fill factor pixel unit. It can make the device more sensitive and less noisy.

(2) High dynamic range (64 dB for single slope integration). The dynamic range can be further improved when dual slope integration or multi-slope integration is used.

(3) On-chip output amplifier with adjustable gain and offset, which can limit the signal jitter to within the input range of the on-chip 10b ADC.

(4) On-chip 40 MHz 10 bit ADC. It can directly perform analog/digital conversion on the output analog signal. The ADC is electrically separated from the image sensor. If necessary, the analog signal can be directly output without analog/digital conversion.

(5) Random windowing mode and sub-sampling mode. The random windowing mode can read out only the area of ​​interest; the sub-sampling mode can well meet the needs of image compression.

(6) On-chip timing and control logic sequencer and internal registers. It allows designers to use fewer signals to control the operation of the sensor.

1.2 Working Principle

IBIS5-B-1300 has 12 registers inside, which provide the parameters and working modes required for the sensor to work. The data written to the register determines the working state of the sensor. There are three interfaces for writing data to the register: parallel interface, serial three-wire interface, and serial two-wire interface. Different data interface modes can be selected by connecting different values ​​to the IF_MODE and SER_MODE pins of the chip (as shown in Table 1).

The parallel interface uses 16-bit parallel input to load new register values. The serial 3-wire interface (or serial-to-parallel interface) uses a serial interface to shift data into the register buffer. When the complete data word is shifted into the register buffer, the data word is loaded into the register currently being encoded. The serial 2-wire interface is a unidirectional interface and will not be analyzed in this article.

IBIS5-B-1300 has two shutter modes: rolling shutter and synchronous shutter, which are set using bit 0 of register (0000). "1" is rolling shutter and "0" is synchronous shutter. The timing is shown in Figure 1 and Figure 2.

In rolling shutter mode, the frame rate Frame period = (Nr. Lines × (RBT + Pixel Period * Nr. Pixels)).

In the synchronous shutter mode, the frame rate is Frame period="Tint"+Tread out="Tint"+(Nr. Lines×(RBT+Pixel Period×Nr. Pixels)). Among them, Tint is the integration (exposure) time; Nr. Lines is the number of lines read out per frame; Nr. Pixels is the number of pixels read out per line; RBT is the line blanking time (typical value is 3.5 ms); Pixel Period is 1/40 MHz="25" ns.

There are two y-direction shift registers in the rolling shutter, one pointing to the row being read out, and the other pointing to the row being reset. The two pointers are driven by the same clock y_clock (row clock), and the difference between them represents the light integration time. In rolling shutter mode, the reading and resetting of pixels are performed simultaneously, and the reset and reading of each row of pixels are performed sequentially (see Figure 3). The pixel integration time can be modified by the register INT_TIME. In this mode, pixels are sensitive to light at different times, so blurring will occur when capturing dynamic images.

In the synchronous shutter mode, the light integration of all pixels is performed at the same time. All pixels are reset at the same time. After light integration, the pixel value is stored in the storage node of each pixel and then read out row by row. The light integration and readout of the pixel are serial. When the pixel is read out, the integration is prohibited, thus avoiding the problem of dynamic image blur caused by the rolling shutter. In addition, the synchronous shutter supports multi-slope integration, which can obtain a higher dynamic range than the rolling shutter.

To sum up, when using this imager chip, the shutter mode should be selected according to the application. When capturing fast-moving objects or requiring a high dynamic range, a synchronous shutter should be selected; when a high frame rate is required for the image or continuous image acquisition is required, a rolling shutter should be selected.

2 Design of CMOS control timing based on FPGA

2.1 Field Programmable Gate Array FPGA

With the development of integrated circuits, large-scale programmable logic devices are widely used in the field of circuit design. They have the characteristics of low power consumption and high reliability, and greatly reduce the size of circuit boards. The internal structure of FPGA determines the superiority of FPGA in timing design. This design uses Xilinx's Spartan3 series FPGA chip XC3$50 as the hardware design platform. Spar-tan3 is based on VirtexⅡFPGA architecture, adopts 90 nm technology, 8-layer metal process, embedded hard-core multiplier and digital clock management module. Structurally, it perfectly combines logic, memory, digital operation, digital processor, I/O and system management resources, making it have a higher level and wider application.

2.2 Design of control timing

The design uses VHDL hardware description language. According to the top-down design method, the timing control part is divided into three modules: reset module, register configuration module and shutter module. Since there are two configuration modes for registers and two shutter modes, the latter two parts can be further divided into two small modules. The three large modules have a strict sequence relationship. The next module can only be started after the previous module has been completed. Figure 4 shows the division of modules and their relationship.

The reset module is used to generate the SYS_RE_SET signal required by the image sensor, so that the sensor can be reset normally, the internal registers can be cleared, and preparation can be made for the configuration of the registers.

The register configuration module is used to configure the 12 registers inside the image sensor and provide the parameters and modes required for the sensor to work. The parameters include integration time, integration mode (single slope or multi-slope), clock interval of X sequence generator, clock interval of SS sequence generator, subsampling mode, window position and size, etc.

The shutter module is used to generate some control signals required for the sensor to work, and to provide the required timing control signals for different shutter modes. In the design of the synchronous shutter, the design adopts a single slope integration, and multi-slope integration is easy to implement based on this design.

The design uses VHDL to program the timing of each module. The shutter module uses a state machine to realize the transition between states (Figure 5 shows the state transition diagram of the rolling shutter module, and Figure 6 shows the state transition diagram of the synchronous shutter). The global clock and ADC clock are implemented using DCM, the digital clock management unit.

3 Experimental Results

3.1 Simulation Results

After the timing control circuit is designed, it is necessary to perform functional simulation, logic synthesis, and post-synthesis simulation on each part, and finally perform synthesis, layout and routing on the entire system to complete the timing simulation. After programming and simulating each module, load each module into the main function top, and use parallel register configuration to simulate the rolling shutter and synchronous shutter modes. The simulation results in Modelsim are shown in Figures 7 and 8.

3.2 Imaging results

This driving timing is applied to the camera system, and the discrimination target and still life are photographed in full-frame output mode (1 280×1 024). The experimental results are shown in Figures 9 and 10. It can be seen from the photographed results that the image is clear and stable without obvious deformation, and the CMOS image sensor meets the imaging requirements.

4 Conclusion

The correctness of the image sensor driving timing plays a decisive role in whether it can work properly. Based on the analysis of the working timing of the CMOS image sensor IBIS5-B-1300, this paper designs two register configuration schemes and two shutter modes, and uses the digital clock management unit (DCM) embedded in the FPGA to complete the design of the system clock and ACD clock. The experimental results show that the designed driving timing can meet the driving requirements of the image sensor.