Design of pulse width detection circuit based on CMOS dual D flip-flop CD4013

The conventional use of D flip-flops is generally as a frequency divider, counter or shift register. However, as long as the peripheral circuit of the D flip-flop is improved, according to its basic logic function, its unique role can be fully utilized. The pulse width detection circuit commonly used in digital devices identifies the width of the pulse signal. For example, when the width of the input pulse is a specific value, a response is generated, otherwise no response is given. The following is an introduction to several pulse width detection circuits composed of CMOS dual D flip-flop CD4013.
      　　One of the detection circuits is shown in Figure 1. IC1 and IC2 are a piece of CD4013, in which IC1 constitutes a monostable flip-flop, the monostable output terminal Q1 serves as the clock pulse of the D flip-flop IC2, and the Q2 terminal serves as the vo output terminal. Since the set S terminals of ICl and IC2 are grounded, the Ql terminal of ICl is always zero in steady state, the Ql terminal is high level, and the VO output is low level. When the Vi input signal is high, the high level of the D1 terminal is sent to the ICl trigger, the Q1 terminal jumps to a high level, the Q1 terminal is low, the quasi-stable state begins, the IC2 trigger is not triggered, and VO is still low. When Vi is low, the quasi-stable state of the ICl monostable circuit has not ended (see Figure 2b), the IC2 trigger has not been triggered, and VO is low. When the quasi-stable state of ICl ends, the ICl trigger is reset, the Q1 terminal is low, and the Q1 terminal is high. Although the CL2 terminal of IC2 is high. However, since the Vi input signal is already low at this time, the reset terminal R2 of IC2 is high after being inverted by the inverter F, so the VO terminal is still low.
      　　Another situation is: when Vi is high and the Q1 terminal is low, the ICl quasi-stable state begins and VO is low. When the temporary stable state of ICl ends, Vi is still at a high level (see Figure 2a), Ql jumps up, IC2 triggers flipping, R2 is at a low level, the high level of D2 is sent to IC2, and VO outputs a high level. When Vi jumps down, F makes R2 of IC2 a high level, forcing IC2 to reset. VO outputs a low level.
      　　It can be seen that only when the pulse width of the Vi input signal is greater than the monostable output pulse width of ICl. IC2 trigger has an output.
      　　The second detection circuit is shown in Figure 3. This circuit is similar to Figure 1, except that the Vi input signal is inverted by inverter F and used as the CL2 clock pulse of IC2. ICl is still a monostable circuit. In steady state, V0 is low level. When Vi is high level, Ql is high level, the temporary stable state begins, IC2 is not triggered, and V0 is low level. When the monostable state of ICl ends (see Figure 4b), Ql returns to a low level, and Vi is still high level at this time, so VO is low level. When Vi jumps down, the F inversion makes the LC2 end of IC2 jump up, but because the Ql end, that is, the R2 end of ZC2, is at a high level, VO is still at a low level.
      　　Another situation is: when Vi is at a high level, Ql is at a high level, ICl's temporary steady state starts, IC2 is not triggered, and V0 is at a low level. When Vi looks down, the temporary steady state has not ended, the Q1 end is still at a low level, IC2 triggers and flips, and VO outputs a high level (see Figure 4a). When the temporary steady state of the ICl monostable circuit ends, the Ql end jumps up to a high level, forcing IC2 to reset, and VO outputs a low level. It can be seen that only when the pulse width of the Vi input signal is less than the monostable output pulse width of ICl. The IC2 trigger has an output.