A design scheme for ultra-low dropout CMOS linear regulator

With the popularity of mobile devices such as laptops, mobile phones, and PDAs, the development of integrated circuits corresponding to various battery power sources has become increasingly active, and high-performance, low-cost, and ultra-small package products are accelerating commercialization. LDO (low dropout) linear regulators have been widely used in portable electronic products due to their simple structure, low cost, low noise, and small size.

In portable electronic products, higher power efficiency means longer battery life, and linear regulator efficiency = output voltage × output current / input voltage × input current × 100%. Therefore, the lower the input and output voltage difference and the lower the quiescent current (the difference between input current and output current), the higher the operating efficiency of the linear regulator.

The output voltage of the low-dropout linear regulator designed in this paper is 2.5V or adjustable, which meets the requirements that when the load is 1mA, the minimum input-output voltage difference is 0.4mV, when the load is 300mA, the voltage difference is 120mV, and the power supply voltage operating range is 2.5~6V.

Circuit structure and working principle

The circuit structure of the low-dropout linear regulator is shown in Figure 1. The circuit consists of a regulator, a bandgap reference voltage, an error amplifier, a fast start-up, an overcurrent limit, an overheat protection, a fault detection, and a sampling resistor network. It also has functions such as enabling and adjustable output. As a load device for the voltage difference, the regulator must meet the requirements of this design. Its selection needs to be considered: first, the transistor and the MOS tube are compared. Since the transistor is a current-controlled device and the MOS tube is a voltage-controlled device, the static current of the MOS tube structure is relatively lower. Secondly, the NMOS tube requires a drive signal higher than the output voltage when working, while the PMOS tube does not have this requirement. It becomes more difficult to generate a high drive voltage, especially at low input voltage. Therefore, this article uses the PMOS tube as the regulator.

Figure 1 Low dropout linear regulator circuit structure

The working principle of the circuit is: during the power-on process of the circuit, there is a 500μA current source in the fast start circuit to charge the bypass capacitor C at the CC end, so that the circuit can be powered on and started as soon as possible. The non-inverting end of the error amplifier samples the output voltage V0 through the sampling resistors R1 and R2, and then outputs the amplified signal after comparing it with Vref, and controls and adjusts the gate voltage of the PMOS tube to keep the output voltage V0 stable, that is:

When the circuit has overcurrent or overheat during operation, the overcurrent limit and overheat protection circuit will respond quickly, the conduction state of the adjustment tube will be weakened and turned off, and the circuit will not be damaged. At the same time, the fault detection circuit will generate a low-level signal. When the enable terminal is connected to a high level, the circuit works normally; when the enable terminal is at a low level, the reference circuit and the adjustment PMOS tube are turned off, and the circuit is in a waiting state.

Key feature analysis and design considerations

1. Dropout voltage (VDO) and quiescent current (Iq)

The dropout voltage is defined as the minimum input-output voltage difference to maintain the normal operation of the regulator. It is an important factor reflecting the adjustment ability of the regulator. For the circuit using PMOS tube as the adjustment tube, the dropout voltage is determined by the on-resistance (Ron) and the load current (Io), that is: VDO = Io×Ron. The quiescent current of the low-dropout linear regulator is the difference between the input current and the output current, that is: Iq = Ii -Io. The quiescent current is composed of the bias current and the gate drive current of the adjustment tube. For the PMOS adjustment tube, the gate is driven by voltage and almost no power consumption is generated. When the regulator carries a small load or no load, the dropout voltage is extremely low, and the quiescent current is equal to the total bias current when the regulator is working. When designing, pay attention to making the on-resistance and leakage current of the PMOS adjustment tube as small as possible, so that each module circuit can work normally under low current conditions.

2. Power consumption (Pw) and efficiency (η)

The power consumption of a low dropout linear regulator is the difference between the input energy and the output energy, that is:

PW = VI II - VO IO = (VI - VO) IO + VI Iq

In the above formula, the first term is the power consumption of the adjustment tube, and the second term is the static current power consumption. As mentioned above, the efficiency of the voltage regulator can be expressed as:

η= IO VO / ( IO + Iq ) VI×100 %

The expression of power consumption and efficiency fully illustrates that for low voltage dropout linear regulator, low dropout voltage and low quiescent current mean low power consumption and high efficiency.

3. Load adjustment capability and voltage adjustment capability

Load regulation capability refers to the ability of the output voltage to maintain a certain value when the output current changes, and is defined as: ΔVO / ΔIO. It represents the ability of the voltage regulator to maintain the output at the nominal value when the load changes. The smaller the value, the better. Voltage regulation capability refers to the ability of the output voltage to maintain a certain value when the input voltage changes. It is defined as: ΔVO / ΔVI. It represents the ability of the voltage regulator to maintain the output at the nominal value when the input voltage changes. The smaller the value, the better. For the circuit structure of Figure 1, its load regulation capability and voltage regulation capability are:

Among them, gm is the transconductance of the adjustment tube; Aod is the open-loop differential mode gain of the error amplifier; Rds is the equivalent resistance between the source and drain of the adjustment tube; RL is the load resistor; R1 and R2 are sampling resistors. It can be seen from the above formula that the key to reducing ΔVO÷ΔIO and ΔVO÷ΔVI is to increase gm and Aod as much as possible.

4. Transient response

Transient response is a dynamic characteristic of the voltage regulator. It refers to the transient pulse phenomenon of the output voltage caused by a step change in the load current and the time it takes for the output voltage to return to stability. It is related to the output capacitor COUT, the equivalent series resistance RESR of the output capacitor, and the bypass capacitor Cb. The maximum transient voltage pulse value ΔVTR(MAX) is:

Where: IO(MAX) refers to the maximum load current that undergoes a step change; Δt1 is the response time of the regulator closed loop, which is related to the regulator closed loop bandwidth (0dB frequency point). When designing an application, it is necessary to consider reducing the transient voltage pulse of the regulator, that is, increasing the bandwidth of the regulator, increasing the output and bypass capacitors, and reducing their equivalent resistance.

5. Output accuracy

The output accuracy of the voltage regulator is the result of the combined effect of multiple factors at the output end, including the output change ΔVLR caused by input voltage change, the output change ΔVLDR caused by load change, the output change ΔVref caused by reference drift, the output change ΔVamp caused by error amplifier offset, the output change ΔVres caused by sampling resistor drift, and the output change ΔVTC caused by operating temperature change. The output accuracy ACC is given by the following formula:

Among them, ΔVref, ΔVamp and ΔVres have a greater impact on ACC, so the topology of the reference voltage source, error amplifier and sampling resistor network needs to be considered during design.

Circuit design and simulation results

1. Design of bandgap reference voltage source

The reference voltage source is the core module of the linear regulator and the most important factor affecting the accuracy of the regulator. The working principle of the bandgap reference voltage source is to use the negative temperature coefficient of the VBE of the transistor and the positive temperature coefficient of the ΔVBE between the two transistors under different current densities, multiplying them by a suitable coefficient to compensate each other, thereby obtaining an output voltage with low temperature drift.

The circuit implementation is shown in Figure 2, with:

Where n is the ratio of the emitter area of ​​Q1 to Q2. Hspice simulation results show that when the power supply voltage changes between 2.5 and 6 V, VREF = 1.254 V at room temperature, and the temperature changes between -30 and 120 ° C, the temperature drift coefficient is less than 10 × 10-6 / ° C.

Figure 2 Bandgap reference circuit 2. Design of error amplifier

The error amplifier compares and amplifies the difference signal between the output feedback sampling voltage and the reference voltage, and controls the conduction state of the adjustment tube after output to keep Vout stable. Its gain, bandwidth, input offset voltage and other indicators have a great influence on the output accuracy, load and voltage adjustment capabilities, transient response and other characteristics of the regulator. The circuit implementation is shown in Figure 3. Through Hspice simulation, it is found that when VCC1 is 4.2V, the input offset voltage of the error amplifier is 0.05μV, the DC gain is 110dB, and the bandwidth reaches 10MHz.

Figure 3 Error amplifier circuit

3. Design of overcurrent limiting module

The design idea of ​​the overcurrent limiting circuit is to control the gate voltage of the adjustment tube by sampling the gate-source voltage of the adjustment tube, thereby achieving the purpose of limiting the output current. The circuit implementation is shown in Figure 4.

Figure 4 Overcurrent limiting circuit

When the load current increases from a small value, VDrv decreases, and the ID of the adjustment tube MTG increases. The gate-source voltage of the adjustment tube MTG is sampled by M20, so that the gate voltage of M31 increases, and the gate voltage of M21 decreases accordingly, thereby adjusting VDrv. Through Hspice simulation, it is found that when the load current exceeds 330mA, M21 will start to conduct, thereby increasing VDrv and reducing the conduction degree of the adjustment tube MTG, which plays a role in current limiting protection.

3.4 Design of overheat protection module

The design idea of ​​the overheat protection circuit is to use temperature-sensitive components to detect changes in the temperature within the chip. When the temperature exceeds the set value, the protection circuit is activated and the adjustment tube is turned off to prevent it from being damaged. The circuit implementation is shown in Figure 5.

Figure 5 Overheat protection circuit

Taking advantage of the negative temperature coefficient of the transistor's VBE, Q0 is used as a temperature measuring element, and a comparator is formed by M12, M13, M10, M5, and M4, and a voltage divider circuit is formed by M11, R1, and R2. When the temperature is lower than the set value, VGM12 and VGM13 are designed, the comparator is reversed, VGM3 becomes a high level, and the output of TOUT is a low level, thereby shutting down the adjustment tube. The temperature protection setting value of this circuit is 160℃, and the simulation results of Hspice are shown in Figure 6, where × represents the output voltage VOUT, ⊙ represents VGM12, Δ represents VGM13, and the load current is 300mA.

Figure 6 Output voltage changes with temperature (I0=300mA)

3.5 Overall circuit simulation results

This circuit adopts the 0.6μm process model of Hyundai Company of South Korea, and simulates and optimizes the overall circuit and key modules through Hspice. The simulation results under typical working conditions are shown in Table 1. The changes of output voltage with input voltage and temperature are shown in Figures 6 and 7. The simulation results fully verify the correctness of the design.

Figure 7 Output voltage changes with input voltage (IO = 300mA)

4 Summary

This paper analyzes and discusses the operating characteristics and design considerations of low-dropout linear regulators, and gives the circuit design diagram of key modules. The simulation results of HSPICE verify that the circuit has good characteristics. The circuit is implemented using standard CMOS technology and has high practical value.