n schemes for off-chip FIash memory IAP

introduction

　　Embedded application systems with ARM chips as processor cores have gained more and more popularity due to their small size, low power consumption, low cost, high performance, rich on-chip resources and wide support for operating systems. Including industrial control, wireless communication, network applications, consumer electronics, imaging and security products, etc., nowadays, the application of ARM microprocessors and embedded technology has penetrated almost into various fields. Among them, ARM7, as a member of the ARM microprocessor series, is a low-power 32-bit RISC processor. Samsung's S3C4510B, Philips' LPC20XX, LPC21XX, LPC22XX series, etc. are all ARM7 processors. These numerous ARM7 processors have their own strengths due to their different on-chip peripherals, but they all use the same ARM7TDMI core (or ARM7TDMI-S core, which is a comprehensive version of ARM7TDMI. There is no difference between these two cores for processor application personnel). It can be said that ARM7TDMI is currently the most widely used 32-bit embedded RISC processor. The ARM7TDMI core uses the von Neumann architecture. The memory used by the processor does not distinguish between data and program instructions. The memory unit pointed to by the PC register, whether it is the ROM area or the RAM area, can be executed as long as it conforms to the format of the ARM instruction, which makes it possible for the system to self-modify. In-Application Programming (IAP) is such a self-modifying program. It first writes the data value in the RAM memory, then makes the PC point to the storage segment and executes the segment as a program segment. Many ARM7 chips have their own IAP processors. Using their own IAP processors, it is convenient to perform in-application programming on the Flash memory integrated in the chip, but almost all ARM core chips do not support off-chip IAP processing, because the off-chip Flash memory is selected by the user, and the chip manufacturer cannot foresee it. The programming timing of different Flash memories is also different, which makes it impossible for chip manufacturers to provide universal IAP codes. So, how to perform in-application programming on the off-chip Flash memory of embedded systems? There are two situations here: one is that the normal code is stored in a separate Flash outside the chip, and the IAP code is completed in another Flash. At this time, you only need to execute the IAP code according to the operation sequence of the Flash to complete the erase or write operation. Although this situation is simple, it uses two Flashes; and the IAP code is very small and can generally be integrated into one chip, so this situation is not considered here. The other situation is that one Flash needs to store both normal code and IAP. The following takes Phnips' LPC2210 and Silicon storage Technology's SST39VFl60 as examples to discuss the IAP solution in detail.

　　1 Hardware Structure

　　1.1 Introduction to LPC2210

　　Philips' LPC2210 is a microcontroller based on the 16/32-bit ARM7TDMI-SCPU that supports real-time simulation and embedded tracing. The chip uses a 144-pin package, has 16 KB on-chip static RAM, and an open external bus; the external memory can be configured into 4 groups through the external memory interface, with a capacity of up to 16 Mb per group and data widths of 8/16/32 bits; it has multiple 32-bit timers, 8-way 10-bit PWM outputs, multiple serial interfaces (including 2 16C550 industrial standard UARTs, high-speed I2C interfaces, and 2 SPI interfaces) and 9 external interrupts, up to 76 general-purpose I/O ports that can withstand 5 V voltage, and an embedded real-time clock and watchdog. The on-chip peripherals are rich and powerful; the on-chip crystal oscillator frequency range is 1 to 30 MHz, and the maximum CPU operating frequency of 60 MHz can be achieved through the on-chip PLL. It has two low-power modes - idle and power-down. The processor is awakened from the power-down mode through external interrupts, and power consumption can be optimized by enabling/disabling external functions individually. The above features make it particularly suitable for industrial control, medical systems, access control and POS machines. It is also very suitable for communication gateway protocol converters, embedded soft modems, and various other types of applications.

　　1.2 SST39VFl60 Introduction

　　The SST39VF160 from Silicon Storage Technology is a 1M×16b CMOS multi-function Flash device that operates with a single voltage for read and write operations over a voltage range of 3.0 to 3.6 V. It is available in 48-pin TSOP and 48-pin TFBGA packages.

　　The main operations of this device include read, word programming, sector/block erase and chip erase operations. Erasing and word programming must follow a certain timing. Table 1 lists the sector erase and word programming process and timing. Reading the trigger bit DQ6 during the erase or program operation will result in a cyclic jump of "1" and "0"; and reading DQ6 after the operation is completed will result in an unchanged fixed value. This is the write operation status detection software method provided by the device.

　　1.3 Hardware Connection

　　SST39VF160 is used as the system program memory, and LPC2210's CSO is used as the chip select signal of Flash. After the processor configures the Boot pin to a 16-bit data bus width, the code in SST39VF160 can be directly executed after power-on. This Flash chip has a 16-bit data width and no byte control bus, so the BLS pin of LPC2210 is not used in the application. The system structure diagram is shown in Figure 1.

　　2 Software Implementation

　　2.1 Analysis of Key Points of IAP Implementation

　　In embedded application systems, it is usually required to record some on-site sensing and interactive input data, and the data is usually recorded in the Flash memory so that the previous data can be obtained next time the power is turned on. If the system program and data are stored separately, then it is sufficient to program the Flash device that stores the data. However, in most embedded systems, the program and the data to be saved coexist in the same Flash memory. So, can the Flash memory be directly programmed as mentioned above? Both theory and practice show that it is not possible. First, calculate theoretically: the chip core operating frequency (CCLK) range allowed by LPC22lO is 10-60 MHz, and the memory read access length is controlled by the read access length field control WSTl in the memory group configuration register BCFG. The maximum available length is 35 CCLKs, and the typical sector erase time of SST39VFl60 is 18 ms. The following is the calculation formula:

　　TRDmax=RDLenmax/CCLKmin=35/10×10-6=3.5 μs

　　．TD=18 ms》3.5μs

　　Where: TRDmax—maximum read access time;

　　RDLenmix – Maximum available length for read access;

　　CCLKmin——minimum core operating clock frequency;

　　Tp——Typical time for sector erase.

　　The formula shows that the typical time of sector erasing is much longer than the maximum read access time. In this way, if data is written to a Flash and prefetched at the same time, the data prefetched must be uncertain data on its data pin because the Flash does not respond to other operations during the execution of the command, and the prefetch fails. Practice also shows that if the same Flash is sector erased during program execution, it will definitely cause a prefetch interrupt.

　　In order to solve the problem of storing programs and IAP in the same Flash chip, the idea of ​​code remapping is introduced. The so-called remapping is that the code is first copied to the specified storage area, and then jumps to the starting point of the specified area to start execution. Here, the lAP program is first copied to the SRAM on the LPC2210 chip, and then jumps to the SRAM to execute the lAP code. As mentioned earlier, ARM7 is a von Neumann structure, which makes it possible to remap the IAP program.

　　The key to writing remappable code is to solve the problem of relative offset in the program. The instructions involving relative offset in the ARM7 instruction series mainly include LDR/STR and jump instructions. The solution here is: all instructions involving offset values ​​use base addressing mode, with the PC register as the base register and the immediate value as the offset. In this way, when the entire program block is moved, the offset value between the data to be loaded or the address to be jumped and the current PC value is fixed, solving the relative offset problem.

　　2.2 Sector Erase

　　The program pre-programmed in Flash is first copied to the specified location of SRAM, and then PC is assigned as the starting point ERASEPART of the sector programming code segment in SRAM. The program starts to execute at the starting point of ERASEPART in SRAM, and starts erasing according to the timing requirements of SST39VF160 sector erasure. According to the ATPCS regulations proposed by ARM, when a C language program calls an assembly program, registers R0 to R3 pass parameters, and the return value is passed by register RO. A parameter of the sector erase program, the sector number to be erased, is passed by RO; the return parameter is placed in R0, and the sector erase is successfully returned "1", otherwise it returns "0".

　　2.3 Word Programming

　　The program starts to execute at the PROGRAMPART starting point in SRAM and starts programming according to the timing requirements of SST39VFl60 word programming. There are three entry parameters, namely programming address, data starting address, and programming data length. If word programming is successful, it returns "1", otherwise it returns "0".

　　3 Conclusion

　　In embedded application systems, IAP is an extremely effective technology. According to the scheme proposed in this paper, in actual applications, only the specific erase and write operation codes for the selected Flash can be changed to realize the in-application programming of the system's off-chip memory. The method proposed in this paper to re-enter the IAP code into the SR-kM for execution effectively solves the IAP problem of embedded systems using 32-bit ARM processors without on-chip program memory, and has great application value.