Single chip multi-microcomputer system sharing RAM circuit

At present, it has been applied in many aspects, such as industrial robot control, CNC machine tool control, etc. Therefore, communication between multiple machines has become the key technology of multi-machine systems. Especially in situations where there are special requirements for data transmission, communication problems between multiple machines must be solved. For example, in the control of industrial robots, there are the following requirements for data transmission: ① The master and slave machines need to share a lot of data; ② The master and slave machines need to exchange information quickly. Under such special requirements, traditional serial and parallel communications are difficult to meet the requirements. The use of multi-machine circuits can not only meet the requirements, but also has the advantages of simplicity, reliability, and good versatility.

1. Circuit principle

Figure 1-87 shows the actual circuit diagram. The shared RAM in the picture is 6264. It has 8 data buses (Do~D7), 13 address buses (Ao~A12), 4 control buses (WR, OE, CS, CS), and 2 power lines. When two microcomputer systems share RAM, they must be isolated with a buffer. When a certain machine needs to be occupied, one machine is connected and the other machine is isolated; otherwise, both machines will fail at the same time. In the circuit shown in Figure 1-87, the buffer is 74LS245, which is an 8-bit bidirectional buffer. Because the 6264 has a total of 24 buses, it uses six 74LS245 and one 74LS125 tri-state gate. 74LS245 has a direction control terminal DIR and a permission terminal G. DIR is directly connected to RD or connected to a fixed potential (+5 V, 0 V). When used for data line buffering, DIR should be connected to RD; when used for address lines and control lines, DIR should be connected to a fixed potential (+5 V, 0 V). In general CPU, the RD signal always appears behind the address signal, such as 8080, 8031, etc. If G is connected to RD, RAM data will be written or read before it is ready, and the system will malfunction. Therefore, it is more appropriate for G to be connected to the decoding end of the system.

The system shares RAM and separates it with a buffer. There is also a problem: if two machines use RAM at the same time, a conflict will occur and both machines will malfunction. The solution is to set up another status trigger, as shown in Figure 1-88. Using a D-type flip-flop in 74LS74, when a computer is ready to use the shared RAM, first test the output terminal Q of the flip-flop. If Q=O, it means that the RAM status is idle; then, the microcomputer issues a set Q=1 command , indicating that the RAM has been used; after it is used up, the microcomputer issues a Q=O command to make the RAM idle and can be used by other microcomputers.

The address of shared RAM varies in different systems. This depends on the decoded address, that is, the same memory location has different addresses for different systems.

From the above analysis, it can be seen that this kind of multi-machine shared RAM circuit only needs to use three processes of query, state setting and clearing the respective RAMs when two machines exchange large blocks of data. Therefore, for large block data exchange, the transmission rate is higher than Traditional serial and parallel are much higher.