Analysis of JESD204 Standard: Why Should We Pay Attention to It?

A new converter interface is steadily gaining in usage and is poised to become the standard for converters in the future. This new interface, JESD204, was created a few years ago and has been gaining traction as a converter interface with higher efficiency through several revisions. As converter resolution and speed increase, the need for a more efficient interface grows. The JESD204 interface provides this efficiency, offering speed, size, and cost advantages over CMOS and LVDS interface offerings. Designs using JESD204 have a higher interface rate, which supports the higher sample rates of converters. Additionally, the reduced pin count results in smaller packages and less wiring, which makes board design easier and reduces overall system cost. The standard can be easily adapted to meet future needs, as evidenced by the two revisions it has gone through. Since its release in 2006, the JESD204 standard has been updated twice and is currently in revision B. As the standard has been adopted by a growing number of converter vendors, users, and FPGA manufacturers, it has been refined and new features have been added to improve efficiency and ease of implementation. This standard applies to both analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), and more importantly, as a common interface for FPGAs (and possibly ASICs).

JESD204 – What is it?

In April 2006, the initial version of JESD204 was released. This version describes a multi-Gbit serial data link between a converter and a receiver (usually an FPGA or ASIC). In the initial version of JESD204, the serial data link was defined as a single serial lane between one or more converters and a receiver. Figure 1 provides a graphical illustration. The lane in the figure represents the physical interface between M converters and receivers, which consists of differential pairs using current mode logic (CML) drivers and receivers. The link shown is the serial data link between the converter and the receiver. The frame clock is sent to both the converter and the receiver and provides the clock for the JESD204 link between the devices.

 
Figure 1. Original JESD204 standard.

The lane data rates are defined between 312.5 Mbps and 3.125 Gbps, with source and load impedances defined as 100 Ω ±20%. The differential level is defined as nominally 800 mV peak-to-peak, with common-mode levels ranging from 0.72 V to 1.23 V. The link utilizes 8b/10b encoding with an embedded clock, which eliminates the need for an additional clock line and the complexity of aligning the transmitted data with an additional clock signal at high data rates. As the JESD204 standard began to be used, it was realized that the standard needed to be revised to support multiple, aligned serial lanes with multiple converters to meet the increasing speed and resolution of converters.

This realization led to the release of the first revision of JESD2004, JESD204A, in April 2008. This revision added the ability to support multiple aligned serial lanes with multiple converters. The supported lane data rates for this revision remain from 312.5 Mbps to 3.125 Gbps, and the frame clock and electrical interface specifications are preserved. The addition of support for multiple aligned serial lanes allows converters with high sample rates and high resolution to reach the maximum supported data rate of 3.125 Gbps. Figure 2 graphically represents the added functionality of the JESD204A revision, which supports multiple lanes. 

 
Figure 2. First Edition – JESD204A

While both the original JESD204 standard and the revised JESD204A standard offer higher performance than older interface standards, they are still missing a key element: deterministic latency of the serial data on the link. For converters, understanding the timing relationship between the sampled signal and its digital representation is critical to correctly reconstructing the analog domain sampled signal when it is received (although this is for ADCs, the situation is similar for DACs). This timing relationship is affected by the converter's latency, which for ADCs is defined as the number of clock cycles from the moment the input signal sampling edge occurs until the converter outputs the digital signal. Similarly, for DACs, latency is defined as the number of clock cycles from the moment the digital signal enters the DAC until the analog output begins to transition. The JESD204 and JESD204A standards do not define a feature that explicitly sets the latency of the converter and its serial digital input/output. In addition, converters continue to increase in speed and resolution. These factors led to the second revision of the standard, JESD204B. In
July 2011, the second revision was released and is known as JESD204B, the current version. One of the important aspects of the revised standard is the inclusion of provisions for achieving deterministic latency. In addition, data rate support has been increased to 12.5 Gbps and is divided into different speed grades for devices. This revised standard uses the device clock as the primary clock source instead of the frame clock as in the previous version. Figure 3 shows the new features in the JESD204B version.

 
Figure 3. Second (Current) Revision – JESD204B

In the two previous revisions of the JESD204 standard, there were no provisions to ensure deterministic latency through the interface. The JESD204B revision provides a mechanism to ensure that latency is reproducible and deterministic between power-up cycles and during link resynchronization. One mechanism is to use the SYNC~ input signal at a well-defined moment to initiate the initial lane alignment sequence of converters in all lanes simultaneously. Another mechanism is to use the SYSREF signal, a new signal defined by JESD204B. The SYSREF signal serves as the master timing reference to align the internal divisions of all device clocks, as well as their local multiframe clocks in each transmitter and receiver. This helps ensure deterministic latency through the system. The JESD204B specification defines three device subclasses: Subclass 0 – no support for deterministic latency; Subclass 1 – deterministic latency using SYSREF; and Subclass 2 – deterministic latency using SYNC~. Subclass 0 can be easily compared to a JESD204A link. Subclass 1 was originally targeted at converters operating at 500MSPS or above, while Subclass 2 was originally targeted at converters operating below 500MSPS. 

In addition to defining latency, JESD204B supports lane data rates up to 12.5 Gbps and divides devices into three different speed grades: Source and load impedances are the same for all three speed grades, defined as 100 Ω ±20%. The first speed grade is the same lane data rate as defined by the JESD204 and JESD204A standards, which means the lane data electrical interface rate is up to 3.125 Gbps. The second speed grade of JESD204B defines an electrical interface with lane data rates up to 6.375 Gbps. This speed grade reduces the minimum differential level for the first speed grade from 500 mV p-p to 400 mV p-p. The third speed grade of JESD204B defines an electrical interface with lane data rates up to 12.5 Gbps. The minimum differential level required for the electrical interface for this speed grade is reduced to 360 mV p-p. As the lane data rates of the different speed grades increase, the minimum required differential level is reduced by reducing the required driver slew rate, making the physical implementation simpler.

To provide more flexibility, the JESD204B revision uses a device clock instead of a frame clock. In previous revisions of JESD204 and JESD204A, the frame clock was the absolute time reference for the JESD204 system. The frame clock and converter sample clock were usually the same. This did not allow for enough flexibility and introduced unnecessary complexity to the system design when the same signal had to be sent to multiple devices and the skew between the different paths was counted. In JESD204B, the device clock is used as the time reference for each element of the JESD204 system. Each converter and receiver receives a separate device clock generated by a clock generator circuit that generates the clocks for all devices from the same source. This allows for more flexibility in system design, but the relationship between the frame clock and the device clock must be specified for each given device.

JESD204 – Why should we care?

Just as LVDS began to replace CMOS as the digital interface technology of choice for converters a few years ago, JESD204 is expected to evolve in a similar manner over the next few years. Although CMOS technology is still in use today, it has been largely replaced by LVDS. The speed and resolution of converters, as well as the need for lower power consumption, will eventually make CMOS and LVDS unsuitable for converters. As the data rate of CMOS outputs increases, the transient current will also increase, resulting in higher power consumption. Although the current and power consumption of LVDS remain relatively flat, the maximum speed that the interface can support is limited. This is due to the driver architecture and the many data lines that must all be synchronized to a data clock. Figure 4 shows the different power requirements for CMOS, LVDS, and CML outputs of a dual-channel 14-bit ADC. 

 
Figure 4. Power consumption comparison of CMOS, LVDS, and CML drivers.

At about 150 – 200 MSPS and 14-bit resolution, CML output drivers begin to become more efficient in terms of power consumption. The advantage of CML is that it requires fewer output pairs for a given resolution than LVDS and CMOS drivers because of the serialization of the data. There is an additional advantage to CML drivers as described by the JESD204B interface specification because the specification requires reduced peak-to-peak voltage levels as the sampling rate increases and increases the output line rate. Likewise, the number of pins required for a given converter resolution and sampling rate is greatly reduced. Table 1 shows the pin count for three different interfaces using a 200 MSPS converter with various channel counts and bit resolutions. In the CMOS and LVDS outputs, the data is used as a synchronization clock for the data in each channel, and the maximum data rate for JESD204B data transmission is 4.0 Gbps when using CML outputs. From this table, it can be seen that the advantage of JESD204B using CML drivers is very clear, with a significant reduction in pin count.

ADI, the industry’s leading data converter supplier, foresaw the trend toward JESD204 (defined by JEDEC) for converter digital interfaces. ADI has been involved in the definition of the JESD204 specification since the initial release. To date, ADI has released several converter products with JESD204 and JESD204A compliant outputs, and is currently developing products with JESD204B compliant outputs. The AD9639 is a quad, 12-bit, 170/210 MSPS ADC with an integrated JESD204 interface. The AD9644 and AD9641 are 14-bit, 80/155 MSPS, dual/single ADCs with an integrated JESD204A interface. On the DAC side, the recently released AD9128 is a dual, 16-bit, 1.25 GSPS DAC with an integrated JESD204A interface. For more information on ADI’s JESD204 compliant products, visit www.analog.com/jesd204

As converter speeds and resolutions increase, the need for more efficient digital interfaces grows. The industry began to realize this with the invention of the JESD204 serial data interface. The interface specification is still evolving to provide a better and faster way to transfer data between converters and FPGAs (or ASICs). The interface has been improved and implemented through two revisions to accommodate the growing demand for higher speed and resolution converters. Looking at the development trend of converter digital interfaces, it is clear that JESD204 is expected to become the industry standard for digital interfaces to converters. Each revision has met the requirements for improving its implementation and allowed the standard to evolve to adapt to changes in converter technology and the new requirements that result. As system designs become more complex and the performance requirements for converters increase, the JESD204 standard should be able to be further adjusted and evolved to meet the needs of new designs.

References

JEDEC Standard: JESD204 (April 2006). JEDEC Solid State Technology Association, website www.jedec.org
JEDEC Standard: JESD204A (April 2008). JEDEC Solid State Technology Association, website www.jedec.org
JEDEC Standard: JESD204B (July 2011). JEDEC Solid State Technology Association. Website www.jedec.org

About the Author

Jonathan Harris is a product applications engineer in the High Speed ​​Converter Group at Analog Devices in Greensboro, NC. He has been an applications engineer supporting products in the RF industry for over 7 years. Jonathan received his MSEE from Auburn University and BSEE from the University of North Carolina at Charlotte. Contact: jonathan.harris@analog.com