Technology for sampling high-speed images using low-speed A/D converters

One obvious area that requires high-speed A/D converters is PC image digital generation. While general TV images have fairly low bandwidth and can sample synthetic YUV signals at 13.5MHz or PAL or NTSC composite video at multiples of the subcarrier frequency (4×), PC image digitization requires higher rates. Conventional CRT monitors receive analog signals, but LCD monitors provide a pixel display and in order to produce a full-screen image need to be driven by a digital signal of the same resolution as the flat panel display, although the straightforward solution is to use the same or higher maximum pixel rate A/D converter with high clock rate, but this article gives two methods of using lower speed converter.

sampling rate

Table 1 lists the rates of some display formats specified by VESA. For example, although the XGA standard goes up to 94.5MHz, most display boards can handle a screen refresh rate of only 75Hz, so the XGA resolution is limited to a 78.5MHz pixel rate.

Table 1 Popular PC image formats

In this case, configuring the PC graphics adapter to produce 85Hz output feels like having to use the frame rate conversion circuitry on the LCD monitor's analog input interface to slow down the rate. System designers do not need to spend extra money to enable 85Hz input on the analog front end because it is not a recommended operating mode.

Assume that an 80MHz converter is used to process a 95MHz input signal. Its cost/performance ratio is more cost-effective than using the more expensive 95MHz ADC. To help understand how to design a system that can accept high-speed input, this article will illustrate the structure of a typical LCD monitor analog front end.

Analog front-end structure

The analog front end includes: PGA (Programmable Gain Amplifier), A/D converter for three color components (R, G, B), PLL to generate pixel clock from line rate, generate LCD panel timing control signal (called is the functional unit of "display timing generator"), the block diagram is shown in Figure 1. To ensure full-screen display of low-resolution images (i.e. VGA on an XGA board), the image needs to be enlarged. An image processor ASIC is typically used to perform the required real-time image scaling. Two-dimensional scaling requires at least one line memory and a fully external frame buffer for data storage. If there are frame rate changes in the system (such as 85Hz ~ 75Hz refresh rate), a full frame buffer is also required. This frame buffer provides great flexibility for data acquisition functions. The memory eliminates the interaction between the display pixel frequency and the pre-analog (data converter) pixel frequency.

By digitally selecting pixels when the pixel frequency is higher than the maximum speed of the A/D converter, the system can be designed to capture data at a speed lower than the pixel frequency. The simple algorithm for this method is to digitize only the odd pixels of each row (at 1/2 the input pixel rate) in the odd pixels of the frame. In the 94.5MHzXGA example, the converter is only required to operate at 48MHz. Capture a complete frame for every two input frames. The framebuffer will hold the previous frame for further processing until the next frame is fully acquired.

It is required to generate a lower sampling clock in the system, which is also beneficial to other functional blocks. For example, the VCO working area of ​​the PLL can be reduced because it only needs to work at 80MHz instead of the original 94.5MHz.

Advantages and Disadvantages

The advantage of this method is that it obtains a full-screen image every two input frames, essentially bisecting the horizontal frequency resolution in time. This will result in artifacts in the image moving horizontally across the target; however, the fact is that for most static image displays the traditional analog PC monitor will be replaced by an LCD monitor, which in the previous example can be digitized with an 80MHz converter for SXGA resolution ( 85Hz refresh rate, 157.5MHz pixel rate) input image only makes sense if the LCD panel can handle such a resolution or uses some other method to reduce the resolution. This principle is only true if a framebuffer can be used for this functionality. Depending on the operating mode, a single memory can store temporary results from the image scaler (pixels below or equal to the maximum speed of the A/D converter) or act as an input buffer to extend the pixel input range of the LCD monitor, which can be discarded Use a calibration engine. Higher pixel rates generally apply to the board's maximum resolution, so no upscaling is required. If there is no frame memory, it still makes sense to use a low-speed A/D.

Parallel ADC

Two converters can be connected in parallel to acquire the input image at full speed, each converter operating only at 1/2 the input pixel rate. If the converter has an output enable function (such as TI's TL V5580 8-bit 80Msps ADC), the output bus can be used as a combined A/D output without the need for an external multiplexer.

For ADCs operating in parallel to match correctly, their digitizing ranges (set by bottom/top reference voltages) should be the same. To ensure this, the corresponding external reference pins on the two ADCs can be tied together. Small tolerance shifts between two ADCs may prevent them from operating in unison, and the same analog input level may be digitized into different output codes in both converters. Note that for a 1Vpp signal, 1LSB of the 8-bit ADC is equivalent to 4mV, so on-board noise is an issue. It is recommended to use separate analog and digital grounds connected at a single point.

automatic calibration

To ensure accuracy, high-end monitors may include automatic calibration features, much like today's high-end CRT monitors that provide color-temperature calibration. In LCDs, known stable input levels are converted to the ADC during the non-active video (horizontal and/or vertical blanking periods) of the image. During this time, the microcontroller monitors the ADC output code and compares it with the desired value. The control loop can adjust the analog input level or the ADC reference level generated by an external DAC. Note that there are analog input level gain and compensation controls for display contrast and brightness level control. Both are user controls available from the LCD monitor front.

Design example

The design shown in Figure 2 is an application example of the principles described in this article. Three TLV5580s are used for XGA@75Hz board type, and the other three TLV5580s are used for high-end SXGA with full-speed sampling. The corresponding references of the two odd-even sampling A/Ds are tied together to prevent intra-channel drift. An 8-output DAC with a microprocessor interface is used to implement the automatic real-standard feature. The A/D value is read during horizontal synchronization (HS) and compared with the desired blanking code. The difference will adjust the top/bottom DAC output of the DAC. The internal bandgap on the A/D is not used to generate the reference, so power saving is achieved through their separate power saving pin (PWDN-REF high state). Note that the maximum clock speed on the board is limited to 1/2 pixel clock in this design. The board interface is "double pixel wide", consisting of two buses for each color component. This significantly reduces EMI and makes PLL design easier. The same PLL circuit can be used in both XGA and SXGA versions. In SXGA the divider in the PLL feedback loop is programmed to half the number of pixels/rows to produce 1/2 the pixel clock frequency. Even and odd clock signals run at the same frequency but in opposite phases.

Conclusion

Although analog LCD interface module design issues are only briefly addressed, it is clear that there are many compromises available, leaving a lot of room for product variation. This article focuses on certain choices in the data converter section and the impact on the overall system design.